/*
  инициализация внутреннего умножителя частоты.
  Вход - 12 МГц, кварцевый резонатор
  внутренняя тактовая - 48 МГц,
  частота генератора - 96 МГц
  Частота сравнения PLL = 12 МГц
*/
static void lowlevel_init_pll_clock_48_xtal12(void)
{
    enum { osc_mul = 8, osc_div = 1 };    // 12 MHz / 1 * 8 = 96 MHz

    // before reprogramming - set safe waitstates
    AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_2FWS;

    ///////////////////////////////////////////////////////////////////////////
    // Init PMC Step 1. Enable Main Oscillator
    // Main Oscillator startup time is board specific:
    // Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms
    // (0x40 for AT91C_CKGR_OSCOUNT field)
    ///////////////////////////////////////////////////////////////////////////
    AT91C_BASE_PMC->PMC_MOR = (((AT91C_CKGR_OSCOUNT & (0x40 << 8)) | AT91C_CKGR_MOSCEN));
    // Wait Main Oscillator stabilization
    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS))
    ;
    ///////////////////////////////////////////////////////////////////////////
    // Init PMC Step 2.
    // Set PLL to 96MHz (96,109MHz) and UDP Clock to 48MHz
    // PLL Startup time depends on PLL RC filter: worst case is choosen
    // UDP Clock (48,058MHz) is compliant with the Universal Serial Bus
    // Specification (+/- 0.25% for full speed)
    ///////////////////////////////////////////////////////////////////////////
    AT91C_BASE_PMC->PMC_PLLR =
                        AT91C_CKGR_USBDIV_1 |
                        AT91C_CKGR_OUT_0 |
                        (AT91C_CKGR_PLLCOUNT & (16 << 8)) |        // PLL lock signalling delay
                        (AT91C_CKGR_MUL & ((osc_mul - 1) << 16)) |
                        (AT91C_CKGR_DIV & osc_div);        
    
    // Wait for PLL stabilization
    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK))
    ;
    
    // Wait until the master clock is established for the case we already
    // turn on the PLL
    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
    ;

    ///////////////////////////////////////////////////////////////////////////
    // Init PMC Step 3.
    // Selection of Master Clock MCK equal to (Processor Clock PCK) PLL/2=48MHz
    // The PMC_MCKR register must not be programmed in a single write operation
    // (see. Product Errata Sheet)
    ///////////////////////////////////////////////////////////////////////////
    AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;    // тактовая частота процессора 96 / 2 = 48

    // Wait until the master clock is established
    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
    ;

    AT91C_BASE_PMC->PMC_MCKR = (AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK);

    // Wait until the master clock is established
    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
    ;

    // as final stage - set desired waitstates
    AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS; // 1 Wait State to work at 48 MHz
}