library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--*******************************************************************************
entity PciInterf  is
    port (
      RST          : in    std_logic;                      -- Reset    
      CLK          : in    std_logic;                      -- Clock    
      AD           : inout std_logic_vector(31 downto 0);  -- Address/Data Bus
      CBE          : in std_logic_vector(3 downto 0);      -- Command/Byte Enable
      PAR          : inout std_logic;                      -- Parity
      FRAME        : in std_logic;                            -- Transaction Frame
      IRDY         : in std_logic;                            -- Initiator Ready
      TRDY         : inout std_logic;                        -- Target Ready
      DEVSEL       : inout std_logic;                      -- Device Select
      STOP         : inout std_logic;                        -- Stop transaction
      IDSEL        : in    std_logic;                      -- Chip Select
      PERR         : inout std_logic;                        -- Parity Error (s/t/s)
      SERR         : inout std_logic;                        -- System Error (o/d)
      INTA         : inout std_logic;                      -- Interrupt pin (o/d)
        
        COUNTPIN     : in std_logic                          --

    );
end PciInterf;
--*******************************************************************************
architecture Behavioral of PciInterf is

begin


end Behavioral;
--*******************************************************************************

NET "AD<0>"     LOC = "P50"  | IOSTANDARD = PCI33_3;
NET "AD<10>"    LOC = "P34"  | IOSTANDARD = PCI33_3;
NET "AD<11>"    LOC = "P33"  | IOSTANDARD = PCI33_3;
NET "AD<12>"    LOC = "P31"  | IOSTANDARD = PCI33_3;
NET "AD<13>"    LOC = "P30"  | IOSTANDARD = PCI33_3;
NET "AD<14>"    LOC = "P29"  | IOSTANDARD = PCI33_3;
NET "AD<15>"    LOC = "P28"  | IOSTANDARD = PCI33_3;
NET "AD<16>"    LOC = "P25"  | IOSTANDARD = PCI33_3;
NET "AD<17>"    LOC = "P24"  | IOSTANDARD = PCI33_3;
NET "AD<18>"    LOC = "P23"  | IOSTANDARD = PCI33_3;
NET "AD<19>"    LOC = "P22"  | IOSTANDARD = PCI33_3;
NET "AD<1>"     LOC = "P49"  | IOSTANDARD = PCI33_3;
NET "AD<20>"    LOC = "P19"  | IOSTANDARD = PCI33_3;
NET "AD<21>"    LOC = "P18"  | IOSTANDARD = PCI33_3;
NET "AD<22>"    LOC = "P16"  | IOSTANDARD = PCI33_3;
NET "AD<23>"    LOC = "P15"  | IOSTANDARD = PCI33_3;
NET "AD<24>"    LOC = "P12"  | IOSTANDARD = PCI33_3;
NET "AD<25>"    LOC = "P11"  | IOSTANDARD = PCI33_3;
NET "AD<26>"    LOC = "P9"   | IOSTANDARD = PCI33_3;
NET "AD<27>"    LOC = "P8"   | IOSTANDARD = PCI33_3;
NET "AD<28>"    LOC = "P5"   | IOSTANDARD = PCI33_3;
NET "AD<29>"    LOC = "P4"   | IOSTANDARD = PCI33_3;
NET "AD<2>"     LOC = "P48"  | IOSTANDARD = PCI33_3;
NET "AD<30>"    LOC = "P3"   | IOSTANDARD = PCI33_3;
NET "AD<31>"    LOC = "P2"   | IOSTANDARD = PCI33_3;
NET "AD<3>"     LOC = "P47"  | IOSTANDARD = PCI33_3;
NET "AD<4>"     LOC = "P42"  | IOSTANDARD = PCI33_3;
NET "AD<5>"     LOC = "P41"  | IOSTANDARD = PCI33_3;
NET "AD<6>"     LOC = "P40"  | IOSTANDARD = PCI33_3;
NET "AD<7>"     LOC = "P39"  | IOSTANDARD = PCI33_3;
NET "AD<8>"     LOC = "P36"  | IOSTANDARD = PCI33_3;
NET "AD<9>"     LOC = "P35"  | IOSTANDARD = PCI33_3;

NET "CBE<0>"    LOC = "P60"  | IOSTANDARD = PCI33_3;
NET "CBE<1>"    LOC = "P62"  | IOSTANDARD = PCI33_3;
NET "CBE<2>"    LOC = "P202" | IOSTANDARD = PCI33_3;
NET "CBE<3>"    LOC = "P199" | IOSTANDARD = PCI33_3;

NET "CLK"       LOC = "P186" | IOSTANDARD = PCI33_3;
NET "DEVSEL"    LOC = "P68"  | IOSTANDARD = PCI33_3;
NET "FRAME"     LOC = "P203" | IOSTANDARD = PCI33_3;
NET "IDSEL"     LOC = "P14"  | IOSTANDARD = PCI33_3;
NET "INTA"      LOC = "P193" | IOSTANDARD = PCI33_3;
NET "IRDY"      LOC = "P200" | IOSTANDARD = PCI33_3;

NET "PAR"       LOC = "P45"  | IOSTANDARD = PCI33_3;
NET "PERR"      LOC = "P64"  | IOSTANDARD = PCI33_3;
NET "RST"       LOC = "P194" | IOSTANDARD = PCI33_3;
NET "SERR"      LOC = "P63"  | IOSTANDARD = PCI33_3;
NET "STOP"      LOC = "P65"  | IOSTANDARD = PCI33_3;
NET "TRDY"      LOC = "P205" | IOSTANDARD = PCI33_3;


NET "COUNTPIN"  LOC = "P20"  | IOSTANDARD = PCI33_3;

entity PciInterf  is
    port (
      RST          : in    std_logic;                      -- Reset    
      CLK          : in    std_logic;                      -- Clock    
      AD           : inout std_logic_vector(31 downto 0);  -- Address/Data Bus
      CBE          : in std_logic_vector(3 downto 0);      -- Command/Byte Enable
      PAR          : inout std_logic;                      -- Parity
      FRAME        : in std_logic;                            -- Transaction Frame
      IRDY         : in std_logic;                            -- Initiator Ready
      TRDY         : inout std_logic;                        -- Target Ready
      DEVSEL       : inout std_logic;                      -- Device Select
      STOP         : inout std_logic;                        -- Stop transaction
      IDSEL        : in    std_logic;                      -- Chip Select
      PERR         : inout std_logic;                        -- Parity Error (s/t/s)
      SERR         : inout std_logic;                        -- System Error (o/d)
      INTA         : inout std_logic;                      -- Interrupt pin (o/d)

     CVALUE    : out std_logic_vector(7 downto 0);   -- value of counter

--*******************************************************************
entity Counter is
   port (
      RESET, COUNTPIN   : in  std_logic;
      CVALUE            : out std_logic_vector(7 downto 0)
    );      
end Counter;
--*******************************************************************
architecture beh of Counter is
   signal COUNT_VALUE : std_logic_vector(7 downto 0);
begin
    process(RESET,COUNTPIN)
    begin
        if(RESET = '1')then
            COUNT_VALUE <= 0;
        else if(COUNTPIN'event and COUNTPIN = '1') then
            COUNT_VALUE <= COUNT_VALUE +1;
        end if;

    end
CVALUE <= COUNT_VALUE;
end beh;
--*******************************************************************

package CFGSPACE_SET is ......

use WORK.CFGSPACE_SET.all;

  component IBUF is
     port(
         I: in std_logic;
         O: out std_logic
     ); end component;

IB2: IBUF port map(I => IDSEL_p, O => IDSELil);

generic (
    vendorID      : std_logic_vector(15 downto 0) := x"4150";
    deviceID      : std_logic_vector(15 downto 0) := x"0001";
    revisionID      : std_logic_vector(7 downto 0)  := x"90";
    subsystemID  : std_logic_vector(15 downto 0) := x"0000";
       subsystemvID : std_logic_vector(15 downto 0) := x"1172";
    classcodeID  : std_logic_vector(23 downto 0) := x"068000";
    -- BAR&WB_CFG (dont delete)