void DACSetup(void)
    {
    RCC->AHBENR |= RCC_AHBENR_DMA2EN;                    // DMA clock enable
    RCC->APB2ENR |= RCC_APB2ENR_TIM8EN;                    // TIM8 Periph clock enable
    RCC->APB1ENR |= RCC_APB1ENR_DACEN;                    // DAC Periph clock enable

    // TIM8
    TIM8->PSC = 0;                                        // Prescaler = 0
    TIM8->ARR = 18;                                        // Auto reload value (18+1)*80/72 = 21.12 us
    TIM8->CR2 = TIM_CR2_MMS(2);                            // Select the TRGO source

    // DMA
    DMA2_Channel3->CCR = DMA_CCR_PL(3) |
                         DMA_CCR_MSIZE(1) |
                         DMA_CCR_PSIZE(1) |
                         DMA_CCR_MINC |
                         DMA_CCR_CIRC |
                         DMA_CCR_DIR |
                         DMA_CCR_HTIE |
                         DMA_CCR_TCIE;
    DMA2_Channel3->CNDTR = 80;
    DMA2_Channel3->CPAR = (u32)&DAC->DHR12R1;            // Peripheral address, page 45 of RM0008 manual
    DMA2_Channel3->CMAR = (u32)&Sine;                    // DMA 2 channel 4 memory address register
    NVIC->ISER[1]  = 1 << (DMA2_Channel3_IRQChannel & 0x1F); // DMA2 Channel 3 global Interrupt

    // DAC
    DAC->CR = DAC_CR_TSEL1(1)|DAC_CR_TEN1|DAC_CR_BOFF1;    // Trigger = Timer 8 TRGO

      // Enable everything
    DMA2_Channel3->CCR |= DMA_CCR_EN;                    // Enable DMA 2 channel 3
    DAC->CR |= DAC_CR_DMAEN1|DAC_CR_EN1;                 // Enable DAC Channel 1
    TIM8->CR1 |= TIM_CR1_CEN;                            // CEN: Counter enable bit
    }

DMAChannel3_IRQHandler()
    {
    DMA2->IFCR = DMA_IFCR_CTCIF3;
    {
    int volatile xx;
    GPIOA->ODR |= 0x04;
    for(xx=0; xx < 10; ++xx)
        __nop();
    GPIOA->ODR &= ~0x04;
    }
    }