Разрабатывается плата, на которой имеется Cyclone4 GX 150 672FBGA в связке с OMAP-L138. А также питание и обвязка памятью.
Все интервфейсы типа DVI, CAN и прочее планируется сделать на мезонине. И вот начинаются проблемы с питанием банков:
- банк 3,4 - DDR2 1.8V
- банк 7 - DDR2 1.8V
- банк 6 - SRAM 2.5V. Тут задействованы все выводы банка на память. Единственный вопрос - позволит ли ква задействовать все выводы банка?
- банк 3A, 3B, 8A, 8B - refclk для ALTGX, 2.5В. Тут вопросов вроде бы нет, на соответсвующие входы идут LVDS клоки для GX трансмиттеров.
- банк 5, 8 - 1.8V связь с DSP (EMIF, uPP).
Мне нужно как можно больше оставшихся свободных сигналов со всех банков завести на мезонин. Но все равно не достаточно выводов для подключения, скажем DVI. Направшивающийся выход - использовать дифпары. И вот тут проблема - все банки с которых я могу взять дифпары питаются от 1.8V, а для LVDS надо 2.5В. Можно как-то это обойти?
Вопрос второй - на входы clk банков 3-8 завожу LVDS клоки. Поймет ли их плисина или при питании 1.8В нифига? Можно конечно завести с генераторов не LVDS, но не было бы проблем с шумами.
На мезонин пойдут также парочку GX-ов, но я не знаю как на мезонине без плисины преобразовать это в параллельный код...
Полная версия этой страницы: Cyclone IV, стандарты IO
Форум разработчиков электроники ELECTRONIX.ru > Программируемая логика ПЛИС (FPGA,CPLD, PLD) > Работаем с ПЛИС, области применения, выбор
По первому вопросу вижу ответ (не знаю как не заметил). Стандарт HSTL-18. Чё-то не нахожу апнот как там че согласовывать, куда резисторы ставить. И что можно поставить на приемной стороне для преобразования HSTL-18 в параллельный.
QUOTE (torik @ Oct 31 2011, 12:06) 
Мне нужно как можно больше оставшихся свободных сигналов со всех банков завести на мезонин. Но все равно не достаточно выводов для подключения, скажем DVI. Направшивающийся выход - использовать дифпары. И вот тут проблема - все банки с которых я могу взять дифпары питаются от 1.8V, а для LVDS надо 2.5В. Можно как-то это обойти?
Вопрос второй - на входы clk банков 3-8 завожу LVDS клоки. Поймет ли их плисина или при питании 1.8В нифига? Можно конечно завести с генераторов не LVDS, но не было бы проблем с шумами.
Вопрос второй - на входы clk банков 3-8 завожу LVDS клоки. Поймет ли их плисина или при питании 1.8В нифига? Можно конечно завести с генераторов не LVDS, но не было бы проблем с шумами.
Здесь недавно обсуждали и пришли к тому, что для LVDS VCCIO неважен.
Вроде бы для клоков есть VCC_CLKIN ?
Цитата
Вроде бы для клоков есть VCC_CLKIN ?
Только часть клоков. Это как раз банки 3A, 3B, 8A, 8B и их я питаю от 2.5В
Цитата
Здесь недавно обсуждали и пришли к тому, что для LVDS VCCIO неважен.
А в каком документе об этом можно почитать? Попробую сейчас, но думается, что ква заругается.
А с HSTL-18 я погорячился. Во-первых, они поддерживаются только для CLK ног, а во-вторых там сложная схема согласования.
QUOTE (torik @ Oct 31 2011, 14:04)
Только часть клоков. Это как раз банки 3A, 3B, 8A, 8B и их я питаю от 2.5В
А в каком документе об этом можно почитать? Попробую сейчас, но думается, что ква заругается.
А с HSTL-18 я погорячился. Во-первых, они поддерживаются только для CLK ног, а во-вторых там сложная схема согласования.
А в каком документе об этом можно почитать? Попробую сейчас, но думается, что ква заругается.
А с HSTL-18 я погорячился. Во-первых, они поддерживаются только для CLK ног, а во-вторых там сложная схема согласования.
На вскидку
http://www.altera.com/support/kdb/solution...4282010_33.html
http://www.alteraforum.com/forum/showthread.php?t=821
Я сейчас делаю проект с ASIC, где LVDS и VCC 1.8V
Вопрос, позволит ли тебе Quartus назначить LVDS
Напряжения смотри
Table 1–20. Differential I/O Standard Specifications for Cyclone IV Devices
Печально, но ква не дает в банке, где сидят DDR2 подключить LVDS:
Блин, этак придется с одного из банков убирать DDR2 и использовать его для LVDS...
А что касается входных клоков, то похоже нет смысла заводить клок на кучу входных пинов, т.к. в циклоне-4 даже один клок можно подать сразу на все PLL и PLL можно каскадировать и с них же давать клок на ALTGX. А если заводить лишь пару клоков, то можно и без дифф. линий обойтись.
Цитата
Error: Pin lvds1_p is incompatible with I/O bank 7. Pin uses I/O standard LVDS, which has a VCCIO requirement incompatible with that bank's VCCIO setting or its other pins that use VCCIO 1.8V.
Info: Pin ddr2t_a[0] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[1] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[2] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[3] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[4] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[5] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[6] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[7] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[8] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[9] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[10] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[11] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[12] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_ba[0] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_ba[1] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_dm[0] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_dm[1] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_wen in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_rasn in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_casn in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_cke in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_csn in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_odt in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[0] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[1] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[2] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[3] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[4] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[5] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[6] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[7] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[8] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[9] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[10] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[11] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_a[12] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_ba[0] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_ba[1] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_dm[0] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_dm[1] in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_wen in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_rasn in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_casn in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_cke in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_csn in I/O bank 7 uses VCCIO 1.8V
Info: Pin ddr2t_odt in I/O bank 7 uses VCCIO 1.8V
Блин, этак придется с одного из банков убирать DDR2 и использовать его для LVDS...
А что касается входных клоков, то похоже нет смысла заводить клок на кучу входных пинов, т.к. в циклоне-4 даже один клок можно подать сразу на все PLL и PLL можно каскадировать и с них же давать клок на ALTGX. А если заводить лишь пару клоков, то можно и без дифф. линий обойтись.
А SSTL II Differential оно дает использовать вместо LVDS? Имхо, при коротких цепях, когда сигнал не успевает затухнуть до значений, близких к пороговым, замена LVDS на SSTL II не имеет значения.
SSTL только на клоковых входах-выходах. Но я погляжу.
Остается, конечно, еще один вариант, но мне он не нравится: поставить на мезонине еще циклон-4, самый маленький. И сделать таким образом некий расширитель портов. А связь по altgx
Остается, конечно, еще один вариант, но мне он не нравится: поставить на мезонине еще циклон-4, самый маленький. И сделать таким образом некий расширитель портов. А связь по altgx
Ну вообще у DDR2 бывает DQS в виде differential SSTL II, так что есть шансы.
Ну вот к примеру схема включения банка 7.
Как только я добавляю пин fio1 в проект (SSTL-18 или просто 1.8V), ква ругается. Но ошибка не наводит меня на суть проблемы:
Я так понимаю, что он требует, чтобы на каждые 9 последовательно (это как?) идущих пинов был хотя бы один промежуток? Что-то я не разглядел где про это написано.
Как только я добавляю пин fio1 в проект (SSTL-18 или просто 1.8V), ква ругается. Но ошибка не наводит меня на суть проблемы:
Цитата
Error: Cannot place pin ddr2t_dq[2] to location A25
Error: Can't place VREF pin E20 (VREFGROUP_B7_N0) for pin ddr2t_dq[2] of type bi-directional with SSTL-18 Class I I/O standard at location A25
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Cannot place pin ddr2t_dq[4] to location B22
Error: Can't place VREF pin E20 (VREFGROUP_B7_N0) for pin ddr2t_dq[4] of type bi-directional with SSTL-18 Class I I/O standard at location B22
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Can't place VREF pin E20 (VREFGROUP_B7_N0) for pin ddr2t_dq[4] of type bi-directional with SSTL-18 Class I I/O standard at location B22
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Cannot place pin ddr2t_dq[6] to location C22
Error: Can't place VREF pin E20 (VREFGROUP_B7_N0) for pin ddr2t_dq[6] of type bi-directional with SSTL-18 Class I I/O standard at location C22
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Cannot place pin ddr2t_dq[7] to location D22
Error: Can't place VREF pin E20 (VREFGROUP_B7_N0) for pin ddr2t_dq[7] of type bi-directional with SSTL-18 Class I I/O standard at location D22
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Can't place VREF pin E20 (VREFGROUP_B7_N0) for pin ddr2t_dq[7] of type bi-directional with SSTL-18 Class I I/O standard at location D22
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Can't fit design in device
Error: Quartus II 64-Bit Fitter was unsuccessful. 13 errors, 4 warnings
Error: Peak virtual memory: 481 megabytes
Error: Processing ended: Tue Nov 01 09:46:56 2011
Error: Elapsed time: 00:00:06
Error: Total CPU time (on all processors): 00:00:06
Error: Peak virtual memory: 481 megabytes
Error: Processing ended: Tue Nov 01 09:46:56 2011
Error: Elapsed time: 00:00:06
Error: Total CPU time (on all processors): 00:00:06
Error: Quartus II Full Compilation was unsuccessful. 15 errors, 230 warnings
Error: Can't place VREF pin E20 (VREFGROUP_B7_N0) for pin ddr2t_dq[2] of type bi-directional with SSTL-18 Class I I/O standard at location A25
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Cannot place pin ddr2t_dq[4] to location B22
Error: Can't place VREF pin E20 (VREFGROUP_B7_N0) for pin ddr2t_dq[4] of type bi-directional with SSTL-18 Class I I/O standard at location B22
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Can't place VREF pin E20 (VREFGROUP_B7_N0) for pin ddr2t_dq[4] of type bi-directional with SSTL-18 Class I I/O standard at location B22
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Cannot place pin ddr2t_dq[6] to location C22
Error: Can't place VREF pin E20 (VREFGROUP_B7_N0) for pin ddr2t_dq[6] of type bi-directional with SSTL-18 Class I I/O standard at location C22
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Cannot place pin ddr2t_dq[7] to location D22
Error: Can't place VREF pin E20 (VREFGROUP_B7_N0) for pin ddr2t_dq[7] of type bi-directional with SSTL-18 Class I I/O standard at location D22
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Can't place VREF pin E20 (VREFGROUP_B7_N0) for pin ddr2t_dq[7] of type bi-directional with SSTL-18 Class I I/O standard at location D22
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin E20 (VREFGROUP_B7_N0) is used on device EP4CGX150DF27I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Info: Location E20 (pad PAD_359): unused
Info: Location G17 (pad PAD_360): unused
Info: Location H17 (pad PAD_361): Pin ddr2t_a[4] of type output uses SSTL-18 Class I I/O standard
Info: Location A23 (pad PAD_362): Pin ddr2t_a[3] of type output uses SSTL-18 Class I I/O standard
Info: Location B23 (pad PAD_363): Pin ddr2t_a[2] of type output uses SSTL-18 Class I I/O standard
Info: Location D20 (pad PAD_364): Pin ddr2t_a[1] of type output uses SSTL-18 Class I I/O standard
Info: Location D21 (pad PAD_365): Pin ddr2t_a[0] of type output uses SSTL-18 Class I I/O standard
Info: Location H16 (pad PAD_366): Pin fio1 of type output uses SSTL-18 Class I I/O standard
Info: Location J16 (pad PAD_367): Pin fio0 of type output uses SSTL-18 Class I I/O standard
Info: Location E18 (pad PAD_368): Pin ddr2t_odt of type output uses SSTL-18 Class I I/O standard
Info: Location E19 (pad PAD_369): Pin ddr2t_csn of type output uses SSTL-18 Class I I/O standard
Info: Location H15 (pad PAD_370): Pin ddr2t_wen of type output uses SSTL-18 Class I I/O standard
Error: Can't fit design in device
Error: Quartus II 64-Bit Fitter was unsuccessful. 13 errors, 4 warnings
Error: Peak virtual memory: 481 megabytes
Error: Processing ended: Tue Nov 01 09:46:56 2011
Error: Elapsed time: 00:00:06
Error: Total CPU time (on all processors): 00:00:06
Error: Peak virtual memory: 481 megabytes
Error: Processing ended: Tue Nov 01 09:46:56 2011
Error: Elapsed time: 00:00:06
Error: Total CPU time (on all processors): 00:00:06
Error: Quartus II Full Compilation was unsuccessful. 15 errors, 230 warnings
Я так понимаю, что он требует, чтобы на каждые 9 последовательно (это как?) идущих пинов был хотя бы один промежуток? Что-то я не разглядел где про это написано.
QUOTE (torik @ Nov 1 2011, 11:07)
Ну вот к примеру схема включения банка 7.
Как только я добавляю пин fio1 в проект (SSTL-18 или просто 1.8V), ква ругается. Но ошибка не наводит меня на суть проблемы:
Я так понимаю, что он требует, чтобы на каждые 9 последовательно (это как?) идущих пинов был хотя бы один промежуток? Что-то я не разглядел где про это написано.
Как только я добавляю пин fio1 в проект (SSTL-18 или просто 1.8V), ква ругается. Но ошибка не наводит меня на суть проблемы:
Я так понимаю, что он требует, чтобы на каждые 9 последовательно (это как?) идущих пинов был хотя бы один промежуток? Что-то я не разглядел где про это написано.
Quartus хочет VREF, т.к. voltage-referenced.
Для предыдущих чипов была глава Pad Placement.
Сейчас там пишут только: юзайте Chip Planner и будет вам
счастье.
Ну это стандартные заморочки, связанные а) с ограничением по шумам на входе VREF, б) с шумами выходов рядом со входами. По-простому это означает, что не нужно так сильно забивать банк. Придется оставить некоторые пады неиспользованными. Причем, что характерно, пады - это не пины. Пады на кристалле, пины на корпусе. В зависимости от корпуса не все пады подключаются к пинам, но вот какие конкретно пины к каким падам прикрепляются, чтобы можно было сказать, что такой-то набор пинов сидит относится к consecutive pads, я не нашел где быстро посмотреть. Просто давал квартусу сначала самому напихать пины в банк, привязывая сигналы к банку. После того, как он говорил, что больше не лезет, начинал утрамбовывание сигналов на тех пинах, что он выбрал: перестановки для лучшей разводки и т.п.
Подобные особенности были еще у Cyclone II.
Подобные особенности были еще у Cyclone II.
Цитата(Hoodwin @ Nov 1 2011, 12:10)
Ну это стандартные заморочки, связанные а) с ограничением по шумам на входе VREF, б) с шумами выходов рядом со входами. По-простому это означает, что не нужно так сильно забивать банк. Придется оставить некоторые пады неиспользованными.
Насколько я слышал, это ограничение можно обойти прописав в констрейнах что все используемые сигналы статические или низкоскоростные. Но сам это не проделывал. Может кто подскажет точнее.
Да, есть свойство, называется что-то вроде toggle_rate, которое управляет расчетом помех, его можно поставить в 0. Но я не думаю, что такой обман целесообразен, если сигналы на самом деле быстрые.
Цитата
Да, есть свойство, называется что-то вроде toggle_rate, которое управляет расчетом помех, его можно поставить в 0. Но я не думаю, что такой обман целесообразен, если сигналы на самом деле быстрые.
А как прописать это для пина?
Цитата(torik @ Nov 6 2011, 23:09)
А как прописать это для пина?
PinPlanner (включите нужную колонку) или Assignament Editor
Цитата(torik @ Nov 7 2011, 07:09)
А как прописать это для пина?
Код
(* chip_pin = "31, 30",
altera_attribute = "-name io_maximum_toggle_rate 0" *)
output [1:0] T1A,
altera_attribute = "-name io_maximum_toggle_rate 0" *)
output [1:0] T1A,
Предпочитаю использовать это в QSF:
Код
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to ov_tp2_data
О я я...
Для просмотра полной версии этой страницы, пожалуйста, пройдите по ссылке.