Код
always @( posedge clk )
begin
if (multiplexer == 4)
out_buf <= a;
else
out_buf<= out_buf + a;
end
always @(posedge clk)
begin
if (multiplexer == 3)
begin
data_valid_reg <=1'b1;
out<=out_buf[g:h];
end
else
begin
data_valid_reg <= 1'b0;
out <= out;
end
begin
if (multiplexer == 4)
out_buf <= a;
else
out_buf<= out_buf + a;
end
always @(posedge clk)
begin
if (multiplexer == 3)
begin
data_valid_reg <=1'b1;
out<=out_buf[g:h];
end
else
begin
data_valid_reg <= 1'b0;
out <= out;
end