`timescale 1ns / 1ps
`include "d:/PROJECTS/UOSON-2/VideoDevKit/Tests/LAN/LANController/EMAC/header.v"
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:56:02 12/02/2011
// Design Name:
// Module Name: LANController
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LANController(Clck125M, Clck100M, Rst, GTxClck, RxClck, RxDV, RxD, RxEr, TxClck, TxEn, TxEr, TxD, LANRst,
Crs, Col, MDIO, MDClck,
TestOut);

input Clck125M;
input Clck100M;
input Rst;
output GTxClck;
input RxClck;
input RxDV;
input [7:0] RxD;
input RxEr;
input TxClck;
output TxEn;
output TxEr;
output [7:0] TxD;
output LANRst;
input Crs;
input Col;
inout MDIO;
output MDClck;
output [7:0] TestOut;

//Ввод-вывод интерфейса управления
wire MDI;
wire MDO;
wire MDIOEn;

//assign MDIO = MDIOEn ? MDO : MDI;
IOBUF #(
.DRIVE(12), // Specify the output drive strength
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) MDIOBUF (
.O(MDI), // Buffer output
.IO(MDIO), // Buffer inout port (connect directly to top-level port)
.I(MDO), // Buffer input
.T(MDIOEn) // 3-state enable input, high=input, low=output
);

reg [7:0] TestOut;
assign LANRst = Rst;

//Управление ядром
wire [2:0] Speed;
reg Rd;
wire RA;
wire [31:0] Data;
reg [15:0] Cntr;
wire MACWA;
reg MACWr;

initial
begin
Cntr = 0;
end

always @(posedge Clck100M)
begin
if (RA) TestOut <= Data[7:0];
Rd <= RA;
end

always @(posedge Clck100M)
begin
if (MACWA) Cntr <= Cntr + 1;
if ((Cntr > 100)&&(Cntr < 2000)) MACWr <= 1;
else MACWr <= 0;
end

MAC_top MAC (
.Reset(!Rst),
.Clk_125M(Clck125M),
.Clk_user(Clck100M),
.Clk_reg(Clck100M),
.Speed(Speed),
.Rx_mac_ra(RA),
.Rx_mac_rd(Rd),
.Rx_mac_data(Data),
.Rx_mac_BE(),
.Rx_mac_pa(),
.Rx_mac_sop(),
.Rx_mac_eop(),
.Tx_mac_wa(MACWA),
.Tx_mac_wr(MACWr),
.Tx_mac_data({16'h0000, Cntr}),
.Tx_mac_BE(2'b00),
.Tx_mac_sop(1'b0),
.Tx_mac_eop(1'b0),
.Pkg_lgth_fifo_rd(Pkg_lgth_fifo_rd),
.Pkg_lgth_fifo_ra(Pkg_lgth_fifo_ra),
.Pkg_lgth_fifo_data(Pkg_lgth_fifo_data),
.Gtx_clk(GTxClck),
.Rx_clk(RxClck),
.Tx_clk(TxClck),
.Tx_er(TxEr),
.Tx_en(TxEn),
.Txd(TxD),
.Rx_er(RxEr),
.Rx_dv(RxDV),
.Rxd(RxD),
.Crs(Crs),
.Col(Col),
.CSB(1'b0),
.WRB(1'b0),
.CD_in(16'h0000),
.CD_out(),
.CA(8'h00),
.Mdo(MDO),
.MdoEn(MDOEn),
.Mdi(MDI),
.Mdc(MDClck)
);

endmodule