WARNING:HDLCompiler:634 - "/home/brainiac/fpga/lab4a/lab4.v" Line 36: Net <leds_var[7]> does not have a driver.
WARNING:Xst:647 - Input <button> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <leds_var> is used but never assigned. This sourceless signal will be automatically connected to value GND.
выход из этого видимо один - переписать код...
но получается порой то же самое...
методом проб и ошибок понял 1 вещь - 1 переменную можно использовать только в 1 блоке always...
а какие есть еще рекомендации?
и как можно переписать код?
Код
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:18:26 11/26/2011
// Design Name:
// Module Name: blink
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fsm(
input clk,
input button,
input reset,
output [7:0] leds
);
localparam [1:0] idle = 2'b00,
wait_a = 2'b01,
ok = 2'b10,
wait_b = 2'b11;
reg [7:0] leds_var_next;
reg [7:0] leds_var;
reg [1:0] state_reg;
reg [1:0] state_next;
reg [23:0] counter_reg;
reg button_var;
reg reset_var;
always @(posedge clk_cmt)
begin
button_var <= button;
reset_var <= reset;
end
always @(posedge clk_cmt)
begin
if (reset_var)
begin
state_reg <= idle;
end
else
begin
state_reg <= state_next;
end
end
always @*
begin
case(state_reg)
idle : begin
if(button_var==1'b1)
begin
state_next <= wait_a;
end
end
wait_a: begin
if(counter_reg >= 20000000)
begin
counter_reg = 24'b0;
state_next <= ok;
end
else
begin
counter_reg = counter_reg + 1'b1;
end
end
ok: if(button_var==1'b0)
state_next <= wait_b;
wait_b: begin
if(counter_reg >= 20000000)
begin
counter_reg = 24'b0;
state_next <= idle;
leds_var = leds_var +1;
end
else
begin
counter_reg = counter_reg + 1'b1;
end
end
default: state_next <= idle;
endcase
end
assign leds = leds_var;
cmt instance_name
(// Clock in ports
.CLK_IN1(clk), // IN
// Clock out ports
.CLK_OUT1(clk_cmt), // OUT
// Status and control signals
.LOCKED(LOCKED));
endmodule
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:18:26 11/26/2011
// Design Name:
// Module Name: blink
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fsm(
input clk,
input button,
input reset,
output [7:0] leds
);
localparam [1:0] idle = 2'b00,
wait_a = 2'b01,
ok = 2'b10,
wait_b = 2'b11;
reg [7:0] leds_var_next;
reg [7:0] leds_var;
reg [1:0] state_reg;
reg [1:0] state_next;
reg [23:0] counter_reg;
reg button_var;
reg reset_var;
always @(posedge clk_cmt)
begin
button_var <= button;
reset_var <= reset;
end
always @(posedge clk_cmt)
begin
if (reset_var)
begin
state_reg <= idle;
end
else
begin
state_reg <= state_next;
end
end
always @*
begin
case(state_reg)
idle : begin
if(button_var==1'b1)
begin
state_next <= wait_a;
end
end
wait_a: begin
if(counter_reg >= 20000000)
begin
counter_reg = 24'b0;
state_next <= ok;
end
else
begin
counter_reg = counter_reg + 1'b1;
end
end
ok: if(button_var==1'b0)
state_next <= wait_b;
wait_b: begin
if(counter_reg >= 20000000)
begin
counter_reg = 24'b0;
state_next <= idle;
leds_var = leds_var +1;
end
else
begin
counter_reg = counter_reg + 1'b1;
end
end
default: state_next <= idle;
endcase
end
assign leds = leds_var;
cmt instance_name
(// Clock in ports
.CLK_IN1(clk), // IN
// Clock out ports
.CLK_OUT1(clk_cmt), // OUT
// Status and control signals
.LOCKED(LOCKED));
endmodule