ldi    RTMPA,OSC_RC32MCREF_bm|OSC_RC2MCREF_bm
    sts    (OSC_DFLLCTRL),RTMPA; set ref. ext. clk

    ldi    RTMPA,DFLL_ENABLE_bm
    sts    (DFLLRC2M_CTRL),RTMPA; enable DFLL RC2
    sts    (DFLLRC32M_CTRL),RTMPA; enable DFLL RC32

void InitRTC()
{
CLKSYS_XOSC_Config(OSC_FRQRANGE_2TO9_gc, false, OSC_XOSCSEL_32KHz_gc);
//TODO: remove this or change access method when new compiler is ready.
volatile uint8_t * p;

//Set internal 32kHz oscillator as clock source for RTC.
p = &CLK.RTCCTRL;
*p = CLK_RTCSRC_TOSC32_gc | CLK_RTCEN_bm;
//// DFLL var XPlain tranning
CLKSYS_Enable( OSC_XOSCEN_bm );
do {} while ( CLKSYS_IsReady( OSC_XOSCRDY_bm ) == 0 );
// RTC var 0
//Configure RTC period to 1 second.
CLKSYS_RTC_ClockSource_Enable(CLK_RTCSRC_TOSC32_gc);
RTC_Initialize(3, 0x0000, 0x0000, RTC_PRESCALER_DIV1_gc);

//Enable overflow interrupt.
RTC_SetIntLevels(RTC_OVFINTLVL_MED_gc, RTC_COMPINTLVL_OFF_gc);
}

void EnableCorrection(void)
{
InitRTC();
////CLKSYS_AutoCalibration_Enable(OSC_RC32MCREF_bm, true);
////CLKSYS_AutoCalibration_Enable(OSC_RC2MCREF_bm, true);
OSC.DFLLCTRL=1;
DFLLRC2M.CTRL|=1;
CLKSYS_AutoCalibration_Enable( OSC_RC2MCREF_bm, true );

/* Due to an errata on ATxmega128A1 we need to enable the 32MHz internal RC oscillator
* and the Autocalibration for the 32MHz internal RC oscillator in order for the calibration
* to work correctly on the 2 MHz internal RC oscillator*/

CLKSYS_Enable( OSC_RC32MEN_bm );
do {} while ( CLKSYS_IsReady( OSC_RC32MRDY_bm ) == 0 );
CLKSYS_AutoCalibration_Enable( OSC_RC32MCREF_bm, true);
}

int main ()
{
EnableCorrection();
}

.NOLIST
.include "ATxmega64A1def.inc"
.LIST
.cseg
.org 0x0000
;----------------------------------
;RTC en
ldi R16,CLK_RTCSRC_TOSC_gc|CLK_RTCEN_bm
sts (CLK_RTCCTRL),R16
;----------------------------------
;XOSC sel
ldi R16,OSC_XOSCSEL_32KHz_gc
sts (OSC_XOSCCTRL),R16
;----------------------------------
;Clock en
ldi R16,OSC_RC2MEN_bm|OSC_RC32MEN_bm|OSC_XOSCEN_bm
sts (OSC_CTRL),R16
;wait ready
lds R17,(OSC_STATUS)
cp R17,R16
brne PC-3
;----------------------------------
;CLKsys RC32M
ldi R16,CCP_IOREG_gc
sts (CPU_CCP),R16
ldi R16,CLK_SCLKSEL_RC32M_gc
sts (CLK_CTRL),R16
;----------------------------------
;DFLL en
ldi R16,OSC_RC32MCREF_bm|OSC_RC2MCREF_bm
sts (OSC_DFLLCTRL),R16
ldi R16,DFLL_ENABLE_bm
sts (DFLLRC2M_CTRL),R16
sts (DFLLRC32M_CTRL),R16
;----------------------------------
;PQ.3->
ldi R16,0x08
sts (PORTQ_DIRSET),R16
;----------------------------------
;Loop 8t
sts (PORTQ_OUTTGL),R16
rjmp PC+1
sts (PORTQ_OUTTGL),R16
rjmp PC-5
;----------------------------------