-- File: output_unit.vhd
-- Engineer: R.
-- Date: 19 June 2011
-- Description:




library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.project_parts.all;


library UNISIM;
use UNISIM.vcomponents.all;





entity output_unit is
-- generic
--(

--);
port
(
-- system clock and reset
clk : in std_logic; -- clock
rst : in std_logic; -- Master reset


C2 : in std_logic;
C3 : in std_logic;

-- master control unit interface

mem_read : in std_logic; --
read_start : in std_logic_vector(15 downto 0);
read_end : in std_logic_vector(15 downto 0);

-- System Memory interface
sysmem_enb : out std_logic;
sysmem_addrb : out std_logic_vector(14 downto 0);
sysmem_doutb_in : in std_logic_vector(63 downto 0);

-- output DDR interface
data_out_p : out std_logic_vector(31 downto 0);
data_out_n : out std_logic_vector(31 downto 0);
datavalid_out_p : out std_logic;
datavalid_out_n : out std_logic;
clk_out_p : out std_logic;
clk_out_n : out std_logic
);
end entity output_unit;



architecture mixed of output_unit is

-- Main Master FSM signals
type outctrl_state is (IDLE, READ_WAIT1, READ_WAIT2, READ,
STATE1,STATE2, STATE3, STATE4, STATE5, STATE6, STATE7, STATE8, STATE9,
STATE10, STATE11, STATE12, STATE13, STATE14, STATE15, STATE16 );
signal outctrl_current, outctrl_next: outctrl_state;


--*****************************************************************************
-- signals for components interconnection
--*****************************************************************************


-- addresses of data points within system memory
signal row_addr : std_logic_vector(15 downto 0);
signal col_addr : std_logic_vector(15 downto 0);
signal preaddr : std_logic_vector(15 downto 0);
signal preaddr_d : std_logic_vector(15 downto 0);
signal preaddr_q : std_logic_vector(15 downto 0);


signal data_counter_start : std_logic_vector(15 downto 0);
signal data_counter_end : std_logic_vector(15 downto 0);
signal data_counter_count : std_logic_vector(15 downto 0);

signal data_counter_en : std_logic; -- sample counter enable
signal data_counter_sclr : std_logic; -- sample counter sync. clear
signal data_counter_value : std_logic_vector(14 downto 0); -- sample cnt. val

signal data_counter_reg_d : std_logic_vector(3 downto 0);
signal data_counter_reg_q : std_logic_vector(3 downto 0);


signal word0_number : std_logic_vector(15 downto 0);
signal word1_number : std_logic_vector(15 downto 0);
signal word0_reg_d : std_logic_vector(15 downto 0);
signal word_control : std_logic;


signal word0_valid : std_logic;
signal word1_valid : std_logic;


signal addr_inc_sel : std_logic_vector(1 downto 0); -- addr. increment mux control signal
signal addr_reg_d : std_logic_vector(10 downto 0);
signal addr_reg_q : std_logic_vector(10 downto 0);

signal data_out0_q : std_logic_vector(31 downto 0);
signal data_out1_q : std_logic_vector(31 downto 0);
signal datavalid_out0_q : std_logic;
signal datavalid_out1_q : std_logic;

signal column_counter_control : std_logic_vector(1 downto 0);

signal s_data : std_logic_vector(63 downto 0); -- two values of sample,32bit

signal out_data_val : std_logic; -- current sample being counted is valid


signal data_out_d : std_logic_vector(63 downto 0);

signal data_out_buf1 : std_logic_vector(31 downto 0);
signal datavalid_out_buf1 : std_logic;

signal clk_out_buf1 : std_logic;

signal read_end_ddr : std_logic_vector(9 downto 0);

signal save_offset : std_logic_vector(1 downto 0); -- save the count offset
signal offset_value_d : std_logic_vector(15 downto 0);
signal offset_value_q : std_logic_vector(15 downto 0);


signal addr_init : std_logic; -- clear the memory row address

signal sysmem_data : std_logic_vector(63 downto 0); -- data from sysmem


signal valid1 : std_logic;
signal valid2 : std_logic;


signal datavalid_out0_q1 : std_logic;
signal datavalid_out1_q1 : std_logic;

signal word0 : std_logic;
signal word1 : std_logic;

attribute keep: string;
attribute keep of preaddr_q: signal is "yes";

begin

--read_end_ddr <= "0" & read_end(9 downto 1);

--=============================================================================
-- Row and Column address computation logic
--=============================================================================
--row and columng address computation
data_counter_start <= std_logic_vector(unsigned(read_start) srl 1);
data_counter_end <= std_logic_vector(unsigned(read_end) srl 1);
data_counter_count <= std_logic_vector(unsigned(data_counter_end) -
unsigned(data_counter_start) - to_unsigned(1,16));



sysmem_addrb <= std_logic_vector(unsigned(data_counter_start(14 downto 0)) +
unsigned(data_counter_value));

--=============================================================================
-- Column Data counter
--=============================================================================
-- this counter counts the values being read from the data row
data_counter: entity work.upcounter
generic map (
WIDTH => 15
)
port map (
clk => clk,
rst => rst,
en => data_counter_en,
sclr => data_counter_sclr,
value => data_counter_value
);




data_out_d <= sysmem_doutb_in;

data_out_reg0: entity work.dffn
generic map (
WIDTH => 32
)
port map (
clk => clk,
rst => rst,
en => '1',
d => data_out_d(63 downto 32),
q => data_out0_q
);

data_out_reg1: entity work.dffn
generic map (
WIDTH => 32
)
port map (
clk => clk,
rst => rst,
en => '1',
d => data_out_d(31 downto 0),
q => data_out1_q
);


data0_valid_reg0: entity work.dff
port map (
clk => clk,
rst => rst,
en => '1',
d => word0_valid,
q => datavalid_out0_q
);

data1_valid_reg0: entity work.dff
port map (
clk => clk,
rst => rst,
en => '1',
d => word1_valid,
q => datavalid_out1_q
);


data0_valid_reg1: entity work.dff
port map (
clk => clk,
rst => rst,
en => '1',
d => datavalid_out0_q,
q => datavalid_out0_q1
);

data1_valid_reg1: entity work.dff
port map (
clk => clk,
rst => rst,
en => '1',
d => datavalid_out1_q,
q => datavalid_out1_q1
);



--=============================================================================
-- control FSM
--=============================================================================
outctrl_fsm: process (outctrl_current, mem_read,
data_counter_value, col_addr, row_addr, word0_number,
read_start, read_end, data_counter_count)
begin
-- state machine default values and output
outctrl_next <= outctrl_current;
data_counter_en <= '0';
data_counter_sclr <= '0';
sysmem_enb <= '0';
word0_valid <= '0';
word1_valid <= '0';

case outctrl_current is

----------------------------- IDLE -----------------------------
-- waiting for an external master start signal to start operation

when IDLE =>

if mem_read = '1' then

--data_counter_en <= '1';
outctrl_next <= STATE1;
else
outctrl_next <= IDLE;
end if;


----------------------------- STATE1 -----------------------------
when STATE1 =>
sysmem_enb <= '1'; -- enable portB of system memory
data_counter_en <= '1';
outctrl_next <= STATE2;

word0_valid <= not read_start(0);
word1_valid <= '1';
----------------------------- STATE2 -----------------------------
when STATE2 =>

word0_valid <= '1';
word1_valid <= '1';


sysmem_enb <= '1'; -- enable portB of system memory
data_counter_en <= '1';
--outctrl_next <= READ;

if unsigned(data_counter_value) >=
unsigned(data_counter_count(14 downto 0)) then

outctrl_next <= STATE3;
else
outctrl_next <= READ;
end if;

----------------------------- READ -----------------------------
when READ =>

word0_valid <= '1';
word1_valid <= '1';

sysmem_enb <= '1'; -- enable portB of system memory
data_counter_en <= '1';


if unsigned(data_counter_value) >=
unsigned(data_counter_count(14 downto 0)) then


outctrl_next <= STATE3;
else
outctrl_next <= READ;
end if;

----------------------------- STATE3 -----------------------------
when STATE3 =>

word0_valid <= '1';
word1_valid <= read_end(0);


data_counter_en <= '1';
data_counter_sclr <= '1';
sysmem_enb <= '1'; -- enable portB of system memory


outctrl_next <= IDLE;


----------------------------- DEFAULT -----------------------------
when others =>
outctrl_next <= IDLE;

end case;
end process;

-- ctrl FSM register
outctrl_fsm_reg: process(clk, rst)
begin
if (rst = '1') then
outctrl_current <= IDLE;
elsif (clk'event and clk = '1') then
outctrl_current <= outctrl_next;
end if;

end process;










--=============================================================================
-- Data output stage
--=============================================================================
output_stage: for index in 31 downto 0 generate
--constant data_hi : natural := index * 32 + 31;
--constant data_lo : natural := index * 32;
begin

OBUFDS_inst_data : OBUFDS
generic map (
IOSTANDARD => "LVDS_33")
port map (
O => data_out_p(index), -- Diff_p output (connect directly to top-level port)
OB => data_out_n(index), -- Diff_n output (connect directly to top-level port)
I => data_out_buf1(index) -- Buffer input
);


ODDR2_inst_data : ODDR2
generic map(
DDR_ALIGNMENT => "C0", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => data_out_buf1(index), -- 1-bit output data
C0 => C2, -- 1-bit clock input
C1 => C3, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => data_out0_q(index), -- 1-bit data input (associated with C0)
D1 => data_out1_q(index), -- 1-bit data input (associated with C1)
R => rst, -- 1-bit reset input
S => '0' -- 1-bit set input
);

end generate output_stage;

--=============================================================================
-- valid output stage
--=============================================================================

OBUFDS_inst_valid : OBUFDS
generic map (
IOSTANDARD => "LVDS_33")
port map (
O => datavalid_out_p,-- Diff_p output (connect directly to top-level port)
OB => datavalid_out_n, -- Diff_n output (connect directly to top-level port)
I => datavalid_out_buf1 -- Buffer input
);


ODDR2_inst_valid : ODDR2
generic map(
DDR_ALIGNMENT => "C0", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => datavalid_out_buf1, -- 1-bit output data
C0 => C2, -- 1-bit clock input
C1 => C3, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => datavalid_out0_q1, -- 1-bit data input (associated with C0)
D1 => datavalid_out1_q1, -- 1-bit data input (associated with C1)
R => rst, -- 1-bit reset input
S => '0' -- 1-bit set input
);



--=============================================================================
-- Clock Forwarding
--=============================================================================

ODDR2_inst_clock : ODDR2
generic map(
DDR_ALIGNMENT => "C0", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clk_out_buf1, -- 1-bit output data
C0 => C2, -- 1-bit clock input
C1 => C3, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => rst, -- 1-bit reset input
S => '0' -- 1-bit set input
);

OBUFDS_inst_clock : OBUFDS
generic map (
IOSTANDARD => "LVDS_33")
port map (
O => clk_out_p, -- Diff_p output (connect directly to top-level port)
OB => clk_out_n, -- Diff_n output (connect directly to top-level port)
I => clk_out_buf1 -- Buffer input
);



end mixed;

-- File: top.vhd
-- Engineer:
-- Date: 8 June 2010
-- Description: This is an upcounter with synchronous enable, clear and
-- asynchronous reset.



library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity upcounter is

generic (
WIDTH: integer := 32 -- width of the value
);
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic; -- count while this signal is high
sclr : in std_logic;
value : out std_logic_vector(WIDTH - 1 downto 0) -- output value

);
end upcounter;


architecture behavioral of upcounter is


-- counter signals
signal value_s : std_logic_vector(WIDTH - 1 downto 0);


begin

value <= value_s;


counter_process: process(clk, rst, sclr)
begin

if rst = '1' then
value_s <= (others => '0');
elsif clk'event and clk = '1' then


if sclr = '1' then
value_s <= (others => '0');
else

if en = '1' then


-- increment value_s
value_s <= std_logic_vector(unsigned(value_s) + to_unsigned(1,WIDTH));




else
value_s <= value_s;
end if;

end if;


end if; -- clock event

end process;

end behavioral;

output_unit_0 : output_unit
port map(
clk    => C2,
rst     => rst,    


C2    => C2,
C3    => C3,
-- master control unit interface

mem_read  => button1_i,
read_start => "0000000000000000",
read_end => "0000000000001111",

-- System Memory interface
sysmem_enb => sysmem_enb,
sysmem_addrb => sysmem_addrb,
sysmem_doutb_in => sysmem_doutb,

-- output  DDR interface
data_out_p => porta_dataout_p,
data_out_n => porta_dataout_n,
datavalid_out_p => porta_datavalid_p,
datavalid_out_n => porta_datavalid_n,
clk_out_p => porta_clk_p,
clk_out_n => porta_clk_n
);