//********************************* ADC_10 **************************************
P6SEL |= BIT0 + BIT1; // Enable A/D channel A0 and A1
ADC10CTL0 = ADC10ON + ADC10SHT_4 + ADC10MSC;

// ADC10ON - ADC10_A on;
// ADC10SHT_8 - ADC10_A sample-and-hold time (256 * 1/5MHz*4) ~200uS
// ADC10MSC - ADC10_A multiple sample and conversion.


ADC10CTL1 = ADC10SHP + ADC10CONSEQ_3 + ADC10SSEL_2 + ADC10DIV_1;

// /*
// ADC10CONSEQ_3 - Repeat-sequence-of-channels
// ADC10SSEL_2 - MCLK
// ADC10DIV_1 - Divide by 2
// ADC10ISSH = 0 - The sample-input signal is not inverted.
// ADC10SHP - SAMPCON signal is sourced from the sampling timer.
// ADC10SHS_0 - ADC10_A sample-and-hold source select (ADC10SC bit)


ADC10CTL2 = ADC10RES;

// ADC10SR - ADC10_A buffer supports up to ~50 ksps.
// ADC10DF = 0 - Binary unsigned format of result
// ADC10RES - 10 bit (12 clock cycle conversion time)
// ADC10PDIV_0 - ADC10 predivider /1


ADC10MCTL0 = 0x01 + ADC10SREF_3; // Two chanell are enabled A0 and A1 + DC10SREF_3 - VR+ = VEREF+ and VR- = AVSS

ADC10IE = 0x01; // Enable ADC10IFG.0

ADC10CTL0 |= ADC10ENC; // Enable conversions

temp = ADC10MEM0;
     if(temp > 512)
          {Synch_1;}
     if(temp < 511)
          {Synch_0;}