function int number_of_bits_for_value_representation(input int value);
  int temp;
  temp    =    2;
  number_of_bits_for_value_representation    =    1;
  while (temp<=value)
    begin
      number_of_bits_for_value_representation = number_of_bits_for_value_representation+1;
      temp  = temp*2;
    end
endfunction

library ieee;
library ieee;
use IEEE.std_logic_1164.all,
IEEE.std_logic_unsigned.all,
IEEE.std_logic_arith.all;

entity dc_fifo is
GENERIC
(
WIDTHA : integer := 8;
WIDTH : integer := 8
);
PORT
(
rst : in std_logic;

wr_clk: in std_logic; -- write clock
wr_ena: in std_logic; -- write clock enable
wr_dta: in std_logic_vector(WIDTH-1 downto 0); -- write data

rd_clk: in std_logic; -- read clock
rd_ena: in std_logic; -- read enable
rd_dta: out std_logic_vector(WIDTH-1 downto 0); -- read data

rd_empty, rd_full, rd_half : out boolean; -- read side status
wr_empty, wr_full, wr_half : out boolean -- write side status
);

end dc_fifo;


architecture behavior of dc_fifo is

constant N : integer := (2**WIDTHA);
constant ADR_MAX : integer := (2**WIDTHA)-1;

subtype ADDRESS is integer range 0 to ADR_MAX;
subtype DATA is std_logic_vector(WIDTH-1 downto 0);
type FIFO_RAM is array (0 to ADR_MAX) of DATA;

-- binary representation of addersses
signal wr_b_adr : ADDRESS;
signal rd_b_adr : ADDRESS;
-- gray code representation of addresses
signal wr_g_adr : ADDRESS;
signal rd_g_adr : ADDRESS;
-- next write signal
signal wr_add : integer range 0 to 1;
signal wr_next : ADDRESS;

signal ram : FIFO_RAM;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : signal is "no_rw_check";


function bin2gray( a : ADDRESS ) return ADDRESS is
variable u, v : std_logic_vector( WIDTHA-1 downto 0 );
variable b : ADDRESS;
begin
v := conv_std_logic_vector( a, WIDTHA );
u := v xor ('0' & v(WIDTHA-1 downto 1));
b := ADDRESS(conv_integer('0' & u));
return b;
end;


function gray2bin( a : ADDRESS ) return ADDRESS is
variable u, v : std_logic_vector( WIDTHA-1 downto 0 );
variable b : ADDRESS;
variable x : std_logic;
begin
v := conv_std_logic_vector( a, WIDTHA );

for i in u'range loop
x := '0';
for j in v'range loop
if (j>=i) then
x := x xor v(j);
end if;
end loop;
u(i) := x;
end loop;

b := ADDRESS(conv_integer('0' & u));
return b;
end;

function fifo_size( w, r : ADDRESS ) return ADDRESS is
constant N : integer := (2**WIDTHA);
variable b : ADDRESS;
begin
b := (N + w - r) mod N;
return b;
end;


begin

wr_add <= 1 when wr_ena='1' else 0;
wr_next <= ( wr_b_adr + wr_add ) mod N;

WRITE_PART:process(rst,wr_clk)
begin

if rst='0' then
wr_b_adr <= 0;
wr_g_adr <= bin2gray( 0 );
wr_empty <= true;
wr_full <= false;
wr_half <= false;
elsif rising_edge(wr_clk) then

-- fix values. Needed for better inferring RAM block
wr_b_adr <= wr_next;
wr_g_adr <= bin2gray( wr_next );

wr_empty <= fifo_size( wr_b_adr, gray2bin(rd_g_adr) ) < 2;
wr_full <= fifo_size( wr_b_adr, gray2bin(rd_g_adr) ) >= N-4;
wr_half <= fifo_size( wr_b_adr, gray2bin(rd_g_adr) ) >= N/2;

end if;
end process;

RAM_STORE:process(wr_clk)
begin
-- perform write, no reset dependency
if rising_edge(wr_clk) then
if wr_ena='1' then
ram(wr_b_adr) <= wr_dta;
end if;
end if;
end process;


READ_PART:process(rst,rd_clk)
begin

if rst='0' then
rd_b_adr <= 0;
rd_g_adr <= bin2gray( 0 );
rd_empty <= true;
rd_full <= false;
rd_half <= false;
elsif rising_edge(rd_clk) then
if rd_ena='1' then
rd_b_adr <= (rd_b_adr+1) mod N;
rd_g_adr <= bin2gray( (rd_b_adr+1) mod N );
end if;
-- fifo status on the reader part
rd_empty <= fifo_size( gray2bin(wr_g_adr), rd_b_adr ) <= conv_integer(rd_ena);
rd_full <= fifo_size( gray2bin(wr_g_adr), rd_b_adr ) >= N-2;
rd_half <= fifo_size( gray2bin(wr_g_adr), rd_b_adr ) >= N/2;
end if;
end process;

RAM_PEEK:process(rd_clk)
begin
-- read register for dual-port RAM inferring
if rising_edge(rd_clk) then
if rd_ena='1' then
rd_dta <= ram(rd_b_adr);
end if;
end if;
end process;


end behavior;

fifo_size( gray2bin(wr_g_adr), rd_b_adr ) <= conv_integer(rd_ena)

wr_b_adr <= gray2bin(wr_g_adr);
rd_empty <= fifo_size( wr_b_adr, rd_b_adr ) <= conv_integer(rd_ena)

DFFE ff0 (.d(Din[0]), .ena(ena), .clk(clk_GN), .q(iDin[0]));
DFFE ff1 (.d(Din[1]), .ena(ena), .clk(clk_GN), .q(iDin[1]));
DFFE ff2 (.d(Din[2]), .ena(ena), .clk(clk_GN), .q(iDin[2]));
DFFE ff3 (.d(Din[3]), .ena(ena), .clk(clk_GN), .q(iDin[3]));

ff[3..0]: dffe;
ff.(d, ena, clk, q) = (Din[3..0], ena, clk_GN, iDin[3..0]);