1. Переменные и функции (взяты из примера по sgdma alterawiki )
#define NUMBER_OF_BUFFERS 1 // количество буферов
#define BUFFER_LENGTH 1152 // длина буфера
// указатель на структуру alt_sgdma_dev
alt_sgdma_dev *receive_DMA;
// Счетчики
alt_u32 buffer_counter = 0, contents_counter = 0, temp_length = BUFFER_LENGTH;
// указатель на текущий заполненый буфер
alt_u32 * receive_ptr;
// массив для выдачи результата
alt_u8 ethmass_ptr[BUFFER_LENGTH + 16];
// Флаг завершения ДМА операции
alt_u8 rx_done = 0;
// Дескрипторы
alt_sgdma_descriptor *receive_descriptors1, *receive_descriptors_copy1;
alt_sgdma_descriptor *receive_descriptors2, *receive_descriptors_copy2;

//---------------------------------------------------------------------------------------------
// Функции

// размещение десрипторов
alt_u32 descriptor_allocation(alt_sgdma_descriptor ** receive_descriptors,
alt_sgdma_descriptor ** receive_descriptors_copy,
alt_u32 number_of_buffers)
{
/* Allocate some big buffers to hold all descriptors which will slide until
* the first 32 byte boundary is found */
void * temp_ptr_2;

/**************************************************************
* Allocation of the receive descriptors *
* - First allocate a large buffer to the temporary pointer *
* - Second check for sucessful memory allocation *
* - Third put this memory location into the pointer copy *
* to be freed before the program exits *
* - Forth slide the tempory pointer until it lies on a 32 *
* byte boundary (descriptor master is 256 bits wide) *
************************************************************/
temp_ptr_2 = malloc((number_of_buffers + 2) * ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE);
if(temp_ptr_2 == NULL)
{
printf("Failed to allocate memory for the receive descriptors\n");
return 1;
}
*receive_descriptors_copy = (alt_sgdma_descriptor *)temp_ptr_2;

while((((alt_u32)temp_ptr_2) % ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE) != 0)
{
temp_ptr_2++; // slide the pointer until 32 byte boundary is found
}
*receive_descriptors = (alt_sgdma_descriptor *)temp_ptr_2;
/**************************************************************/

/* Clear out the null descriptor owned by hardware bit. These locations
* came from the heap so we don't know what state the bytes are in (owned bit could be high).*/
receive_descriptors[number_of_buffers]->control = 0;

return 0; // no failures in allocation
}
//---------------------------------------------------------------------------------------------
/********************************************************************************
**
* This function is responsible for allocating the data buffer for each *
* descriptor. A random buffer length will be generated if you set the minimum *
* and maximum buffer lengths to be different. To run a more controlled test, set *
* the minimum and maximum buffer lengths to be equal. *
* *
* Returns 0 for sucess, 1 for failure. *
********************************************************************************
**/

alt_u32 create_test_data(alt_sgdma_descriptor * receive_descriptors,
alt_u32 number_of_buffers,
alt_u32 buffer_length)
{

alt_u32 buffer_counter, contents_counter, temp_length;
alt_u32 *receive_ptr;
alt_u8 *receive_ptr_copy; // will use these to fill up the tx buffers and clear the rx buffers


/* Initialization of the buffer memories and the transmit+receive descriptors */
for(buffer_counter = 0; buffer_counter < number_of_buffers; buffer_counter++)
{
/* Generate a random buffer length between within MINIMUM_BUFFER_LENGTH and MAXIMUM_BUFFER_LENGTH */
temp_length = buffer_length;

receive_ptr = (alt_u32 *)malloc(temp_length); // since the same contents will be received the length is the same

/* This will populate sequential data (modulo 256) in each transmit buffer a byte at a time.
* The recieve buffers are also cleared with zeros so that each time this software is run
* the data can be reverified. Before this function returns a flush will be performed to
* make sure none of these writes are still in the data cache.
*/
receive_ptr_copy = (alt_u8 *)receive_ptr;

for(contents_counter = 0; contents_counter < temp_length; contents_counter++)
{
receive_ptr_copy[contents_counter] = 0;
}

/* This will create a descriptor that is capable of transmitting data from an Avalon-ST FIFO
* to an Avalon-MM buffer */
alt_avalon_sgdma_construct_stream_to_mem_desc(&receive_descriptors[buffer_counter], // descriptor
&receive_descriptors[buffer_counter+1], // next descriptor
receive_ptr, // write buffer location
(alt_u16)temp_length, // length of the buffer
0); // writes are not to a fixed location

}

alt_dcache_flush_all(); // make sure all the transmit buffers and cleared receive buffers go out to main memory

return 0; // no failures creating data buffers
}

//---------------------------------------------------------------------------------------------
// Обработчик прерываний SGDMA_0_IRQ
static void receive_callback_function(void * context)
{
rx_done++;
if(rx_done > 1) rx_done = 0;

}

//---------------------------------------------------------------------------------------------
// Задержка
void Delay ( tick)
{
while(tick--);
}

int main (void)
{
// Открыть SGDMA
receive_DMA = alt_avalon_sgdma_open("/dev/sgdma_0");
if(receive_DMA == NULL)
{
printf("Could not open the receive SG-DMA\n");
}
else printf("Open the receive SG-DMA... success\n");

// размещение дескрипторов
descriptor_allocation(&receive_descriptors1,
&receive_descriptors_copy1,
NUMBER_OF_BUFFERS);
descriptor_allocation(&receive_descriptors2,
&receive_descriptors_copy2,
NUMBER_OF_BUFFERS);

// создание дескрипторов
create_test_data(receive_descriptors1,
NUMBER_OF_BUFFERS,
BUFFER_LENGTH);
create_test_data(receive_descriptors2,
NUMBER_OF_BUFFERS,
BUFFER_LENGTH);

// определение подпрограммы обработчика прерываний
alt_avalon_sgdma_register_callback(receive_DMA,
&receive_callback_function,
(ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK |
ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK),
NULL);
// главный цикл
while (1)
{
Delay (0.1 сек)

// старт приема по sgdma

if(rx_done)
{
// старт транзации во второй буфер
alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors2[0]);
// пуск пакета N 2 1152 байта из источника (пользовательской логики)
IOWR_ALTERA_AVALON_PUSK(AVSOURCE_0_BASE);
Delay(0x0007);
IOWR_ALTERA_AVALON_STOP(AVSOURCE_0_BASE);
}
else
{
// старт транзации в первый буфер
alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors1[0]);
// пуск пакета N 1 1152 байта из источника (пользовательской логики)
IOWR_ALTERA_AVALON_PUSK(AVSOURCE_0_BASE);
Delay(0x0007);
IOWR_ALTERA_AVALON_STOP(AVSOURCE_0_BASE);
}

// получение результата
for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
{
if(rx_done)
receive_ptr = receive_descriptors1[buffer_counter].write_addr;
else
receive_ptr = receive_descriptors2[buffer_counter].write_addr;
}
for(contents_counter = 0; contents_counter < temp_length; contents_counter++)
{
// массив с результатом
ethmass_ptr[contents_counter + 16] = IORD_8DIRECT((alt_u32)receive_ptr, contents_counter);
... далее выдача по ethenet...
}
}

}

#define NUMBER_OF_BUFFERS 1
#define BUFFER_LENGTH 16
alt_sgdma_descriptor *receive_descriptors1, *receive_descriptors_copy1;
alt_sgdma_descriptor *receive_descriptors2, *receive_descriptors_copy2;
alt_sgdma_descriptor *receive_descriptors_sw, *receive_descriptors_copy_sw;
// если была передача по Ethernet
if(!buff_done)
{
// запуск транзакции в чередной буфер
alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors_sw[0]);
// пуск пакета из пользовательской логики
IOWR_ALTERA_AVALON_PUSK(AVSOURCE_0_BASE);
Delay(0x000f);
IOWR_ALTERA_AVALON_STOP(AVSOURCE_0_BASE);
}
// обработка и посылка пакета из предыдущего буфера
if(buff_done)
{
for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
{
receive_ptr = receive_descriptors_sw[buffer_counter].write_addr;
for(contents_counter = 0; contents_counter < temp_length; contents_counter++)
{
// формирование пакетов COM и Ethernet
chltemp_receive[contents_counter] = 0;
chltemp_receive[contents_counter] = IORD_8DIRECT((alt_u32)receive_ptr, contents_counter);
ethmass_ptr[contents_counter + 16] = chltemp_receive[contents_counter];
}
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, led);
// послать сом и Ethernet пакет
fprintf(fp, chltemp_receive);
eth_ocm_raw_send(ethmass_ptr, sizeof(ethmass_ptr));
}
// пакеты посланы
buff_done = 0;
}

// Обработчик прерываний SGDMA_0_IRQ
static void receive_callback_function(void * context)
{
rx_done++;
if(rx_done > 1) rx_done = 0;
if(rx_done)
{
receive_descriptors_sw = receive_descriptors1;
receive_descriptors_copy_sw = receive_descriptors_copy1;
}
else
{
receive_descriptors_sw = receive_descriptors2;
receive_descriptors_copy_sw = receive_descriptors_copy2;
}

buff_done = 1;
}

// определение подпрограммы обработчика прерываний
  alt_avalon_sgdma_register_callback(receive_DMA,
                                    &receive_callback_function,
                                    (ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK |
                                    ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK),
                                    NULL);

#define NUMBER_OF_BUFFERS 4  
#define BUFFER_LENGTH 16

alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors_sw[0]);

#define NUMBER_OF_BUFFERS 4
#define BUFFER_LENGTH 1152
alt_sgdma_descriptor *receive_descriptors1, *receive_descriptors_copy1;
alt_sgdma_descriptor *receive_descriptors2, *receive_descriptors_copy2;
alt_sgdma_descriptor *receive_descriptors_sw, *receive_descriptors_copy_sw;

alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors_sw[0]);                                                

IOWR_ALTERA_AVALON_PUSK(FIRSOURCE_0_BASE);
Delay(0x0002);
IOWR_ALTERA_AVALON_STOP(FIRSOURCE_0_BASE);
Delay(0x000f);

alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors_sw[0]);

rx_done++;
if(rx_done == 2) rx_done = 0;
if(rx_done)
{
rx_done = 0;
receive_descriptors_sw = receive_descriptors1;
receive_descriptors_copy_sw = receive_descriptors_copy1;
}
else
{
receive_descriptors_sw = receive_descriptors2;
receive_descriptors_copy_sw = receive_descriptors_copy2;
}


for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
{
receive_ptr = receive_descriptors_sw[buffer_counter].write_addr;

// послать Ethernet пакет
ethmass_ptr[15]++;
ethmass_ptr[14] = eth_ocm_raw_send(receive_ptr, 1152);

}

       // старт приема по sgdma

          rx_done = 0;

          receive_descriptors_sw = receive_descriptors1;
          receive_descriptors_copy_sw = receive_descriptors_copy1;

          // чтение регистра управления  
          control = IORD_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_0_BASE);  
          //
          control |= ALTERA_AVALON_SGDMA_CONTROL_PARK_MSK;
          // запись регистра управления
          IOWR_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_0_BASE, control);

          alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors_sw[0]);                                                
          // запуск пакета из пользовательской логики
          IOWR_ALTERA_AVALON_PUSK(FIRSOURCE_0_BASE);
          Delay(0x0002);
          IOWR_ALTERA_AVALON_STOP(FIRSOURCE_0_BASE);
          Delay(0x000f);

  irq_count ++; if(irq_count == 4) irq_count = 0;
  // на последнем прерывании запуск sgdma не делать
  if(irq_count < 4)
    alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors_sw[0]);

  rx_done++;
  if(rx_done == 2) rx_done = 0;
  if(!rx_done)
  {
    receive_descriptors_sw = receive_descriptors1;
    receive_descriptors_copy_sw = receive_descriptors_copy1;
  }
  else
  {
    receive_descriptors_sw = receive_descriptors2;
    receive_descriptors_copy_sw = receive_descriptors_copy2;
  }

  
  for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
  {
    receive_ptr = receive_descriptors_sw[buffer_counter].write_addr;

    // послать Ethernet пакет
    ethmass_ptr[15]++;
     ethmass_ptr[14] = eth_ocm_raw_send(receive_ptr, 1152);

  }

// размещение дескрипторов
return_code = descriptor_allocation(&receive_descriptors1,
&receive_descriptors_copy1,
NUMBER_OF_BUFFERS);
return_code = descriptor_allocation(&receive_descriptors2,
&receive_descriptors_copy2,
NUMBER_OF_BUFFERS);

// создание дескрипторов
return_code = create_test_data(receive_descriptors1,
NUMBER_OF_BUFFERS,
BUFFER_LENGTH);
return_code = create_test_data(receive_descriptors2,
NUMBER_OF_BUFFERS,
BUFFER_LENGTH);

// определение подпрограммы обработчика прерываний
alt_avalon_sgdma_register_callback(receive_DMA,
&receive_callback_function,
(ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK |
ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK),
NULL);

    if(return_code == 1)
    {
        printf("Allocating the data buffers failed... exiting\n");
        return 1;
    }
    else printf("Allocating the data buffers... success\n");

// размещение десрипторов
alt_u32 descriptor_allocation(alt_sgdma_descriptor ** receive_descriptors,
alt_sgdma_descriptor ** receive_descriptors_copy,
alt_u32 number_of_buffers)
{
/* Allocate some big buffers to hold all descriptors which will slide until
* the first 32 byte boundary is found */
void * temp_ptr_2;

/**************************************************************
* Allocation of the receive descriptors *
* - First allocate a large buffer to the temporary pointer *
* - Second check for sucessful memory allocation *
* - Third put this memory location into the pointer copy *
* to be freed before the program exits *
* - Forth slide the tempory pointer until it lies on a 32 *
* byte boundary (descriptor master is 256 bits wide) *
************************************************************/
temp_ptr_2 = malloc((number_of_buffers + 2) * ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE);
if(temp_ptr_2 == NULL)
{
printf("Failed to allocate memory for the receive descriptors\n");
return 1;
}
*receive_descriptors_copy = (alt_sgdma_descriptor *)temp_ptr_2;

while((((alt_u32)temp_ptr_2) % ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE) != 0)
{
temp_ptr_2++; // slide the pointer until 32 byte boundary is found
}
*receive_descriptors = (alt_sgdma_descriptor *)temp_ptr_2;
/**************************************************************/

/* Clear out the null descriptor owned by hardware bit. These locations
* came from the heap so we don't know what state the bytes are in (owned bit could be high).*/
receive_descriptors[number_of_buffers]->control = 0;

return 0; // no failures in allocation
}
//---------------------------------------------------------------------------------------------
/********************************************************************************
**
* This function is responsible for allocating the data buffer for each *
* descriptor. A random buffer length will be generated if you set the minimum *
* and maximum buffer lengths to be different. To run a more controlled test, set *
* the minimum and maximum buffer lengths to be equal. *
* *
* Returns 0 for sucess, 1 for failure. *
********************************************************************************
**/

alt_u32 create_test_data(alt_sgdma_descriptor * receive_descriptors,
alt_u32 number_of_buffers,
alt_u32 buffer_length)
{

alt_u32 buffer_counter, contents_counter, temp_length;
alt_u32 *receive_ptr;
alt_u8 *receive_ptr_copy; // will use these to fill up the tx buffers and clear the rx buffers


/* Initialization of the buffer memories and the transmit+receive descriptors */
for(buffer_counter = 0; buffer_counter < number_of_buffers; buffer_counter++)
{
/* Generate a random buffer length between within MINIMUM_BUFFER_LENGTH and MAXIMUM_BUFFER_LENGTH */
temp_length = buffer_length;

receive_ptr = (alt_u32 *)malloc(temp_length); // since the same contents will be received the length is the same

/* This will populate sequential data (modulo 256) in each transmit buffer a byte at a time.
* The recieve buffers are also cleared with zeros so that each time this software is run
* the data can be reverified. Before this function returns a flush will be performed to
* make sure none of these writes are still in the data cache.
*/
receive_ptr_copy = (alt_u8 *)receive_ptr;

for(contents_counter = 0; contents_counter < temp_length; contents_counter++)
{
receive_ptr_copy[contents_counter] = 0;
}

/* This will create a descriptor that is capable of transmitting data from an Avalon-ST FIFO
* to an Avalon-MM buffer */
alt_avalon_sgdma_construct_stream_to_mem_desc(&receive_descriptors[buffer_counter], // descriptor
&receive_descriptors[buffer_counter+1], // next descriptor
receive_ptr, // write buffer location
(alt_u16)temp_length, // length of the buffer
0); // writes are not to a fixed location

}

alt_dcache_flush_all(); // make sure all the transmit buffers and cleared receive buffers go out to main memory

return 0; // no failures creating data buffers
}