adc_dma=adc_dma_init (
      "/dev/sgdma_0",            // char* sgdma_name
      580,/*1106-для qam, 60000 - для ацп*/                       // int width
      1,                      // int height
      8,                  // int color_depth
      -1,          // int buffer_location (malloc buffers)
      -1,          // int descriptor_location (malloc descriptors)
      4,
      (alt_avalon_sgdma_callback)&qam_recive_int); //4-для qam, 1-для ацп   // int num_buffer

alt_video_display* adc_dma_init( char* sgdma_name,
                                           int width,
                                           int height,
                                           int color_depth,
                                           int buffer_location,
                                           int descriptor_location,
                                           int num_buffers,
                                           alt_avalon_sgdma_callback callbck)//////////////290811
{
  alt_video_display* display;
  unsigned int bytes_per_pixel, bytes_per_frame, descriptors_per_frame, i;
  int result;

  // We'll need these values more than once, so let's pre-calculate them.
  bytes_per_pixel = color_depth >> 3; // same as /8
  bytes_per_frame = (( width * height ) * bytes_per_pixel );

  // Calculate the number of descriptors needed for each frame
  if( bytes_per_frame <= ALT_VIDEO_DISPLAY_BYTES_PER_DESC ) {
    descriptors_per_frame = 1;
  }
  else if(( bytes_per_frame % ALT_VIDEO_DISPLAY_BYTES_PER_DESC) == 0) {
    descriptors_per_frame = bytes_per_frame / ALT_VIDEO_DISPLAY_BYTES_PER_DESC;
  }
  else {
    descriptors_per_frame =
      ( bytes_per_frame / ALT_VIDEO_DISPLAY_BYTES_PER_DESC ) + 1;
  }

  // Check for too many frame buffers
  if( num_buffers > ALT_VIDEO_DISPLAY_MAX_BUFFERS ) {
      num_buffers = ALT_VIDEO_DISPLAY_MAX_BUFFERS;
  }

  // Allocate our display struct
  display = (alt_video_display*) malloc(sizeof(alt_video_display));
  if(!display) {
    return NULL;
  }

  // Fill out the display structure
  display->width = width;
  display->height = height;
  display->color_depth = color_depth;
  display->num_frame_buffers = num_buffers;
  display->bytes_per_frame = bytes_per_frame;
  display->bytes_per_pixel = bytes_per_pixel;
  display->buffer_being_displayed = 0;
  display->buffer_being_written = (num_buffers > 1) ? 1:0;
  display->descriptors_per_frame = descriptors_per_frame;

  // Allocate our frame and descriptor buffers
  if(alt_video_display_allocate_buffers( display,
                                         bytes_per_frame,
                                         buffer_location,
                                         descriptor_location,
                                         num_buffers ) ) {
    return NULL;
  }

  // Now construct SGDMA descriptors for each frame buffer
  for( i = 0; i < num_buffers; i++ ) {
    setup_adc_descriptors(
      display,                                    // our display
      display->buffer_ptrs[i],                    // frame
      display->buffer_ptrs[i]->buffer,            // frame location
      display->buffer_ptrs[i]->desc_base );       // descriptor memory
  }

  // Clear all frame buffers to black
  for( i = 0; i < num_buffers; i++ ) {
    memset( (void*)(display->buffer_ptrs[i]->buffer),
      0, display->bytes_per_frame );
  }

  // Open the SGDMA
  display->sgdma = alt_avalon_sgdma_open(sgdma_name);
  if(!display->sgdma) {
    return NULL;
  }



  /////////////////////290811//////////////////////////
  alt_avalon_sgdma_register_callback(
          display->sgdma,
         callbck,
         (alt_u16)ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK|ALTERA_AVALON_SGDMA_CONTROL_IE_CHA
IN_COMPLETED_MSK,
         (void*)(display));

  /////////////////////////////////////////////////////


  /* Enable SGDMA "parking" mode */
  IOWR_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_0_BASE,
    ALTERA_AVALON_SGDMA_CONTROL_PARK_MSK);

  /* Now start the SGDMA */
  result = alt_avalon_sgdma_do_async_transfer(
    display->sgdma,
    display->buffer_ptrs[display->buffer_being_displayed]->desc_base);

  if(result) {
    return NULL;
  }

  return ( display );
}

unsigned char adc_dma_restart(alt_video_display *display)
{
//    while (IORD_ALTERA_AVALON_SGDMA_STATUS(display->sgdma->base) & ALTERA_AVALON_SGDMA_STATUS_BUSY_MSK);
      /* Enable SGDMA "parking" mode */
    if (!(IORD_ALTERA_AVALON_SGDMA_STATUS(display->sgdma->base) & ALTERA_AVALON_SGDMA_STATUS_BUSY_MSK))
    IOWR_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_0_BASE,
        ALTERA_AVALON_SGDMA_CONTROL_PARK_MSK);

      /* Now start the SGDMA */
return(      alt_avalon_sgdma_do_async_transfer(
        display->sgdma,
        display->buffer_ptrs[display->buffer_being_displayed]->desc_base));
}

// Размер буфера
#define BUFFER_SIZE 1168
int i;

alt_dma_rxchan rxchan;

unsigned char *rx_buffer = (void*)BUFFER_SIZE;

// обнуление приемника
for(i = 0; i < BUFFER_SIZE; i++)
{
rx_buffer[i] = 0;
}


/* Create the receive channel */
if ((rxchan = alt_dma_rxchan_open("/dev/sgdma_0")) == NULL)
{
printf ("Failed to open receive channel\n");
}
else printf ("Open receive channel.. success\n");
alt_dma_rxchan_ioctl(rxchan, ALT_DMA_SET_MODE_8, 0);

// открыть sgdma
alt_sgdma_dev * receive_DMA = alt_avalon_sgdma_open("/dev/sgdma_0");
if(receive_DMA == NULL)
{
printf("Could not open the receive SG-DMA\n");
}
else printf("Open the receive SG-DMA... success\n");

// определение подпрограммы обработчика прерываний
alt_avalon_sgdma_register_callback(receive_DMA,
&receive_callback_function,
(ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK |
ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK),
NULL);

alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors);

// Now construct SGDMA descriptors for each frame buffer
  for( i = 0; i < num_buffers; i++ ) {
    setup_adc_descriptors(
      display,                                    // our display
      display->buffer_ptrs[i],                    // frame
      display->buffer_ptrs[i]->buffer,            // frame location
      display->buffer_ptrs[i]->desc_base );       // descriptor memory

void setup_adc_descriptors(
alt_video_display *display,
alt_video_frame *frame,
alt_u32 *buffer,
alt_sgdma_descriptor *desc_base)
{
int i;
alt_u16 length;
alt_32 buffer_no_cache_bypass;
alt_sgdma_descriptor *last_descriptor;

/*
  * We don't want the "uncached" bit set in the buffer address we hand
  * off to the SGDMA, so we mask it out here.
  */
buffer_no_cache_bypass =
   (alt_u32) alt_remap_cached(buffer, display->bytes_per_frame );

for(i=0; i<display->descriptors_per_frame; i++){
   /*
    * Calculate the data length associated with each descriptor, taking
    * into account the edge cases
    */
   if(i == (display->descriptors_per_frame-1)) {
     length = (display->bytes_per_frame % ALT_VIDEO_DISPLAY_BYTES_PER_DESC);

      /*
       * The init routine calculated the number of desriptors per frame,
       * based on frame size (bytes) and bytes per descriptor. Being evenly
       * divisible on this last frame means a full-length sized frame.
       */
      if(length == 0) {
        length = ALT_VIDEO_DISPLAY_BYTES_PER_DESC;
      }
   }
   else {
     length = ALT_VIDEO_DISPLAY_BYTES_PER_DESC;
   }

   /* Construct the descriptor */
   [b]alt_avalon_sgdma_construct_stream_to_mem_desc(
     (frame->desc_base + i),                    /* Descriptor */
     ( frame->desc_base + i + 1 ),              /* Next descriptor */
     (alt_u32*)( (alt_u8*)buffer_no_cache_bypass +
        (ALT_VIDEO_DISPLAY_BYTES_PER_DESC*i) ), /* Write Address */
     length,                                    /* Transfer length */
     0                                         /* Don't write fixed addr */
    );[/b]

   /*
    * The last descriptor we created above requires a special modification:
    * Its "next" pointer should point back to the first descriptor in the
    * chain to create a loop.
    *
    * This was not done done in the above SGDMA descriptor creation routine
    * call because that routine always terminates the 'next' descriptor
    * pointer to prevent the SGDMA from continuing into unknown memory.
    */
   if( i == ( display->descriptors_per_frame - 1 ) ) {
     last_descriptor = (alt_sgdma_descriptor *) (frame->desc_base + i);

//     IOWR_32DIRECT((alt_u32)(&last_descriptor->next), 0,
//       (alt_u32)(frame->desc_base));
   }
}
}

// открыть sgdma
alt_sgdma_dev * receive_DMA = alt_avalon_sgdma_open("/dev/sgdma_0");
if(receive_DMA == NULL)
{
printf("Could not open the receive SG-DMA\n");
}
else printf("Open the receive SG-DMA... success\n");

alt_sgdma_descriptor *receive_descriptors, *receive_descriptors_copy, *wraddr;

alt_avalon_sgdma_construct_stream_to_mem_desc(
&receive_descriptors, /* Descriptor */
&receive_descriptors_copy, /* Next descriptor */
&wraddr, /* Write Address */
32, /* Transfer length */
0 /* Don't write fixed addr */
);

// старт приема по sgdma
alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors);

/* each direction so double this for the total */
#define NUMBER_OF_BUFFERS 1
#define BUFFER_LENGTH 64
alt_u32 descriptor_allocation(alt_sgdma_descriptor ** receive_descriptors,
alt_sgdma_descriptor ** receive_descriptors_copy,
alt_u32 number_of_buffers);

alt_u32 create_test_data(alt_sgdma_descriptor * receive_descriptors,
alt_u32 number_of_buffers,
alt_u32 buffer_length);

alt_u32 buffer_counter, contents_counter, temp_length = 32;
alt_u32 * receive_ptr;
alt_u8 *temp_receive;
alt_u8 chltemp_receive[33];
// Флаг завершения ДМА операции
static volatile alt_u8 rx_done = 0;
//---------------------------------------------------------------------------------------------
// Функции

// размещение десрипторов
alt_u32 descriptor_allocation(alt_sgdma_descriptor ** receive_descriptors,
alt_sgdma_descriptor ** receive_descriptors_copy,
alt_u32 number_of_buffers)
{
/* Allocate some big buffers to hold all descriptors which will slide until
* the first 32 byte boundary is found */
void * temp_ptr_2;

/**************************************************************
* Allocation of the receive descriptors *
* - First allocate a large buffer to the temporary pointer *
* - Second check for sucessful memory allocation *
* - Third put this memory location into the pointer copy *
* to be freed before the program exits *
* - Forth slide the tempory pointer until it lies on a 32 *
* byte boundary (descriptor master is 256 bits wide) *
************************************************************/
temp_ptr_2 = malloc((number_of_buffers + 2) * ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE);
if(temp_ptr_2 == NULL)
{
printf("Failed to allocate memory for the receive descriptors\n");
return 1;
}
*receive_descriptors_copy = (alt_sgdma_descriptor *)temp_ptr_2;

while((((alt_u32)temp_ptr_2) % ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE) != 0)
{
temp_ptr_2++; // slide the pointer until 32 byte boundary is found
}
*receive_descriptors = (alt_sgdma_descriptor *)temp_ptr_2;
/**************************************************************/

/* Clear out the null descriptor owned by hardware bit. These locations
* came from the heap so we don't know what state the bytes are in (owned bit could be high).*/
receive_descriptors[number_of_buffers]->control = 0;

return 0; // no failures in allocation
}
//---------------------------------------------------------------------------------------------
/********************************************************************************
**
* This function is responsible for allocating the data buffer for each *
* descriptor. A random buffer length will be generated if you set the minimum *
* and maximum buffer lengths to be different. To run a more controlled test, set *
* the minimum and maximum buffer lengths to be equal. *
* *
* Returns 0 for sucess, 1 for failure. *
********************************************************************************
**/

alt_u32 create_test_data(alt_sgdma_descriptor * receive_descriptors,
alt_u32 number_of_buffers,
alt_u32 buffer_length)
{

alt_u32 buffer_counter, contents_counter, temp_length;
alt_u32 *receive_ptr;
alt_u8 *receive_ptr_copy; // will use these to fill up the tx buffers and clear the rx buffers
alt_u32 temp_data = 0;


/* Initialization of the buffer memories and the transmit+receive descriptors */
for(buffer_counter = 0; buffer_counter < number_of_buffers; buffer_counter++)
{
/* Generate a random buffer length between within MINIMUM_BUFFER_LENGTH and MAXIMUM_BUFFER_LENGTH */
temp_length = buffer_length;

receive_ptr = (alt_u32 *)malloc(temp_length); // since the same contents will be received the length is the same

/* This will populate sequential data (modulo 256) in each transmit buffer a byte at a time.
* The recieve buffers are also cleared with zeros so that each time this software is run
* the data can be reverified. Before this function returns a flush will be performed to
* make sure none of these writes are still in the data cache.
*/
receive_ptr_copy = (alt_u8 *)receive_ptr;

for(contents_counter = 0; contents_counter < temp_length; contents_counter++)
{
receive_ptr_copy[contents_counter] = 0;
temp_data++;
}

/* This will create a descriptor that is capable of transmitting data from an Avalon-ST FIFO
* to an Avalon-MM buffer */
alt_avalon_sgdma_construct_stream_to_mem_desc(&receive_descriptors[buffer_counter], // descriptor
&receive_descriptors[buffer_counter+1], // next descriptor
receive_ptr, // write buffer location
(alt_u16)temp_length, // length of the buffer
0); // writes are not to a fixed location

}

alt_dcache_flush_all(); // make sure all the transmit buffers and cleared receive buffers go out to main memory

return 0; // no failures creating data buffers
}
//---------------------------------------------------------------------------------------------
void receive_callback_function(void * context)
{
rx_done++; /* main will be polling for this value being 1 */
}

alt_sgdma_dev *receive_DMA;

// Открыть SGDMA
receive_DMA = alt_avalon_sgdma_open("/dev/sgdma_0");
if(receive_DMA == NULL)
{
printf("Could not open the receive SG-DMA\n");
}
else printf("Open the receive SG-DMA... success\n");

// alt_sgdma_descriptor дескрипторы
alt_sgdma_descriptor *receive_descriptors, *receive_descriptors_copy;
alt_u32 return_code;

// размещение дескрипторов
return_code = descriptor_allocation(&receive_descriptors,
&receive_descriptors_copy,
NUMBER_OF_BUFFERS);
if(return_code == 1)
{
printf("Allocating the descriptor memory failed... exiting\n");
return 1;
}
else printf("Allocating the descriptor memory... success\n");

// определение подпрограммы обработчика прерываний
alt_avalon_sgdma_register_callback(receive_DMA,
&receive_callback_function,
(ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK |
ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK),
NULL);

// старт приема по sgdma

return_code = create_test_data(receive_descriptors,
NUMBER_OF_BUFFERS,
BUFFER_LENGTH);
if(return_code == 1)
{
printf("Allocating the data buffers failed... exiting\n");
return 1;
}
else printf("Allocating the data buffers... success\n");

// запуск SGDMA
if(alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors[0]) != 0)
{
printf("Writing the head of the receive descriptor list to the DMA failed\n");
return 1;
}
else printf("Writing the head of the receive descriptor list to the DMA ... success\n");

// ожидание заполнения дискрипторов
while(rx_done == 0) {}
printf("The receive SGDMA has completed\n");

// получение результата

/* loop through each descriptor */
for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
{
receive_ptr = receive_descriptors[buffer_counter].write_addr;
temp_length = receive_descriptors[buffer_counter].bytes_to_transfer;

/* loop through each buffer to check the contents on each byte */
for(contents_counter = 0; contents_counter < temp_length; contents_counter++)
{
temp_receive = IORD_8DIRECT((alt_u32)receive_ptr, contents_counter);
chltemp_receive[contents_counter] = temp_receive;
chltemp_receive[32] = 0;
fprintf(fp, chltemp_receive);
}
/* Done with these two, time to clean up after ourselves. */
free(receive_ptr);
}

alt_avalon_sgdma_stop(receive_DMA);

free(receive_descriptors_copy);

for(k = 0; k < 31; k++)
uramres[k] = vldt[k];
uramres[32] = 0;

fprintf(fp, uramres);

#define NUMBER_OF_BUFFERS 1  
#define BUFFER_LENGTH 16

/* each direction so double this for the total */
#define NUMBER_OF_BUFFERS 2
#define BUFFER_LENGTH 64
alt_u32 buffer_counter = 0, contents_counter = 0, temp_length = BUFFER_LENGTH;
alt_u32 * receive_ptr;
alt_u8 chltemp_receive[BUFFER_LENGTH];

// Флаг завершения ДМА операции
static volatile alt_u8 rx_done = 0;

//---------------------------------------------------------------------------------------------
// Функции

// размещение десрипторов
alt_u32 descriptor_allocation(alt_sgdma_descriptor ** receive_descriptors,
alt_sgdma_descriptor ** receive_descriptors_copy,
alt_u32 number_of_buffers)
{
/* Allocate some big buffers to hold all descriptors which will slide until
* the first 32 byte boundary is found */
void * temp_ptr_2;

/**************************************************************
* Allocation of the receive descriptors *
* - First allocate a large buffer to the temporary pointer *
* - Second check for sucessful memory allocation *
* - Third put this memory location into the pointer copy *
* to be freed before the program exits *
* - Forth slide the tempory pointer until it lies on a 32 *
* byte boundary (descriptor master is 256 bits wide) *
************************************************************/
temp_ptr_2 = malloc((number_of_buffers + 2) * ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE);
if(temp_ptr_2 == NULL)
{
printf("Failed to allocate memory for the receive descriptors\n");
return 1;
}
*receive_descriptors_copy = (alt_sgdma_descriptor *)temp_ptr_2;

while((((alt_u32)temp_ptr_2) % ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE) != 0)
{
temp_ptr_2++; // slide the pointer until 32 byte boundary is found
}
*receive_descriptors = (alt_sgdma_descriptor *)temp_ptr_2;
/**************************************************************/

/* Clear out the null descriptor owned by hardware bit. These locations
* came from the heap so we don't know what state the bytes are in (owned bit could be high).*/
receive_descriptors[number_of_buffers]->control = 0;

return 0; // no failures in allocation
}
//---------------------------------------------------------------------------------------------
/********************************************************************************
**
* This function is responsible for allocating the data buffer for each *
* descriptor. A random buffer length will be generated if you set the minimum *
* and maximum buffer lengths to be different. To run a more controlled test, set *
* the minimum and maximum buffer lengths to be equal. *
* *
* Returns 0 for sucess, 1 for failure. *
********************************************************************************
**/

alt_u32 create_test_data(alt_sgdma_descriptor * receive_descriptors,
alt_u32 number_of_buffers,
alt_u32 buffer_length)
{

alt_u32 buffer_counter, contents_counter, temp_length;
alt_u32 *receive_ptr;
alt_u8 *receive_ptr_copy; // will use these to fill up the tx buffers and clear the rx buffers


/* Initialization of the buffer memories and the transmit+receive descriptors */
for(buffer_counter = 0; buffer_counter < number_of_buffers; buffer_counter++)
{
/* Generate a random buffer length between within MINIMUM_BUFFER_LENGTH and MAXIMUM_BUFFER_LENGTH */
temp_length = buffer_length;

receive_ptr = (alt_u32 *)malloc(temp_length); // since the same contents will be received the length is the same

/* This will populate sequential data (modulo 256) in each transmit buffer a byte at a time.
* The recieve buffers are also cleared with zeros so that each time this software is run
* the data can be reverified. Before this function returns a flush will be performed to
* make sure none of these writes are still in the data cache.
*/
receive_ptr_copy = (alt_u8 *)receive_ptr;

for(contents_counter = 0; contents_counter < temp_length; contents_counter++)
{
receive_ptr_copy[contents_counter] = 0;
}

/* This will create a descriptor that is capable of transmitting data from an Avalon-ST FIFO
* to an Avalon-MM buffer */
alt_avalon_sgdma_construct_stream_to_mem_desc(&receive_descriptors[buffer_counter], // descriptor
&receive_descriptors[buffer_counter+1], // next descriptor
receive_ptr, // write buffer location
(alt_u16)temp_length, // length of the buffer
0); // writes are not to a fixed location

}

alt_dcache_flush_all(); // make sure all the transmit buffers and cleared receive buffers go out to main memory

return 0; // no failures creating data buffers
}

// Инициализация
alt_sgdma_dev *receive_DMA;

// Открыть SGDMA
receive_DMA = alt_avalon_sgdma_open("/dev/sgdma_0");
// alt_sgdma_descriptor дескрипторы
alt_sgdma_descriptor *receive_descriptors, *receive_descriptors_copy;
alt_u32 return_code;

// размещение дескрипторов
return_code = descriptor_allocation(&receive_descriptors,
&receive_descriptors_copy,
NUMBER_OF_BUFFERS);
// определение подпрограммы обработчика прерываний
alt_avalon_sgdma_register_callback(receive_DMA,
&receive_callback_function,
(ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK |
ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK),
NULL);

// Запуск sgdma и получение результата (для теста все в цикле через 1 секу)

while ....
....
// старт приема по sgdma

return_code = create_test_data(receive_descriptors,
NUMBER_OF_BUFFERS,
BUFFER_LENGTH);
// запуск SGDMA
if(alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors[0]) != 0)
{
return 1;
}

// ожидание заполнения дискрипторов
while(rx_done == 0) {}

// получение результата

/* loop through each descriptor */
for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
{
receive_ptr = receive_descriptors[buffer_counter].write_addr;

/* loop through each buffer to check the contents on each byte */
for(contents_counter = 0; contents_counter < temp_length; contents_counter++)
{
chltemp_receive[contents_counter] = 0;
chltemp_receive[contents_counter] = IORD_8DIRECT((alt_u32)receive_ptr, contents_counter);
}
chltemp_receive[temp_length] = 0;
fprintf(fp, chltemp_receive);
/* Done with these two, time to clean up after ourselves. */
free(receive_ptr);
}

alt_avalon_sgdma_stop(receive_DMA);

free(receive_descriptors_copy);

....

    alt_avalon_sgdma_register_callback(receive_DMA,
                                    &receive_callback_function,
                                    (ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK |
                                    ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK),
                                    NULL);

1. Переменные и функции (взяты из примера по sgdma alterawiki )
#define NUMBER_OF_BUFFERS 1 // количество буферов
#define BUFFER_LENGTH 1152 // длина буфера
// указатель на структуру alt_sgdma_dev
alt_sgdma_dev *receive_DMA;
// Счетчики
alt_u32 buffer_counter = 0, contents_counter = 0, temp_length = BUFFER_LENGTH;
// указатель на текущий заполненый буфер
alt_u32 * receive_ptr;
// массив для выдачи результата
alt_u8 ethmass_ptr[BUFFER_LENGTH + 16];
// Флаг завершения ДМА операции
alt_u8 rx_done = 0;
// Дескрипторы
alt_sgdma_descriptor *receive_descriptors1, *receive_descriptors_copy1;
alt_sgdma_descriptor *receive_descriptors2, *receive_descriptors_copy2;

//---------------------------------------------------------------------------------------------
// Функции

// размещение десрипторов
alt_u32 descriptor_allocation(alt_sgdma_descriptor ** receive_descriptors,
alt_sgdma_descriptor ** receive_descriptors_copy,
alt_u32 number_of_buffers)
{
/* Allocate some big buffers to hold all descriptors which will slide until
* the first 32 byte boundary is found */
void * temp_ptr_2;

/**************************************************************
* Allocation of the receive descriptors *
* - First allocate a large buffer to the temporary pointer *
* - Second check for sucessful memory allocation *
* - Third put this memory location into the pointer copy *
* to be freed before the program exits *
* - Forth slide the tempory pointer until it lies on a 32 *
* byte boundary (descriptor master is 256 bits wide) *
************************************************************/
temp_ptr_2 = malloc((number_of_buffers + 2) * ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE);
if(temp_ptr_2 == NULL)
{
printf("Failed to allocate memory for the receive descriptors\n");
return 1;
}
*receive_descriptors_copy = (alt_sgdma_descriptor *)temp_ptr_2;

while((((alt_u32)temp_ptr_2) % ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE) != 0)
{
temp_ptr_2++; // slide the pointer until 32 byte boundary is found
}
*receive_descriptors = (alt_sgdma_descriptor *)temp_ptr_2;
/**************************************************************/

/* Clear out the null descriptor owned by hardware bit. These locations
* came from the heap so we don't know what state the bytes are in (owned bit could be high).*/
receive_descriptors[number_of_buffers]->control = 0;

return 0; // no failures in allocation
}
//---------------------------------------------------------------------------------------------
/********************************************************************************
**
* This function is responsible for allocating the data buffer for each *
* descriptor. A random buffer length will be generated if you set the minimum *
* and maximum buffer lengths to be different. To run a more controlled test, set *
* the minimum and maximum buffer lengths to be equal. *
* *
* Returns 0 for sucess, 1 for failure. *
********************************************************************************
**/

alt_u32 create_test_data(alt_sgdma_descriptor * receive_descriptors,
alt_u32 number_of_buffers,
alt_u32 buffer_length)
{

alt_u32 buffer_counter, contents_counter, temp_length;
alt_u32 *receive_ptr;
alt_u8 *receive_ptr_copy; // will use these to fill up the tx buffers and clear the rx buffers


/* Initialization of the buffer memories and the transmit+receive descriptors */
for(buffer_counter = 0; buffer_counter < number_of_buffers; buffer_counter++)
{
/* Generate a random buffer length between within MINIMUM_BUFFER_LENGTH and MAXIMUM_BUFFER_LENGTH */
temp_length = buffer_length;

receive_ptr = (alt_u32 *)malloc(temp_length); // since the same contents will be received the length is the same

/* This will populate sequential data (modulo 256) in each transmit buffer a byte at a time.
* The recieve buffers are also cleared with zeros so that each time this software is run
* the data can be reverified. Before this function returns a flush will be performed to
* make sure none of these writes are still in the data cache.
*/
receive_ptr_copy = (alt_u8 *)receive_ptr;

for(contents_counter = 0; contents_counter < temp_length; contents_counter++)
{
receive_ptr_copy[contents_counter] = 0;
}

/* This will create a descriptor that is capable of transmitting data from an Avalon-ST FIFO
* to an Avalon-MM buffer */
alt_avalon_sgdma_construct_stream_to_mem_desc(&receive_descriptors[buffer_counter], // descriptor
&receive_descriptors[buffer_counter+1], // next descriptor
receive_ptr, // write buffer location
(alt_u16)temp_length, // length of the buffer
0); // writes are not to a fixed location

}

alt_dcache_flush_all(); // make sure all the transmit buffers and cleared receive buffers go out to main memory

return 0; // no failures creating data buffers
}

//---------------------------------------------------------------------------------------------
// Обработчик прерываний SGDMA_0_IRQ
static void receive_callback_function(void * context)
{
rx_done++;
if(rx_done > 1) rx_done = 0;

}

//---------------------------------------------------------------------------------------------
// Задержка
void Delay ( tick)
{
while(tick--);
}

int main (void)
{
// Открыть SGDMA
receive_DMA = alt_avalon_sgdma_open("/dev/sgdma_0");
if(receive_DMA == NULL)
{
printf("Could not open the receive SG-DMA\n");
}
else printf("Open the receive SG-DMA... success\n");

// размещение дескрипторов
descriptor_allocation(&receive_descriptors1,
&receive_descriptors_copy1,
NUMBER_OF_BUFFERS);
descriptor_allocation(&receive_descriptors2,
&receive_descriptors_copy2,
NUMBER_OF_BUFFERS);

// создание дескрипторов
create_test_data(receive_descriptors1,
NUMBER_OF_BUFFERS,
BUFFER_LENGTH);
create_test_data(receive_descriptors2,
NUMBER_OF_BUFFERS,
BUFFER_LENGTH);

// определение подпрограммы обработчика прерываний
alt_avalon_sgdma_register_callback(receive_DMA,
&receive_callback_function,
(ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK |
ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK),
NULL);
// главный цикл
while (1)
{
Delay (0.1 сек)

// старт приема по sgdma

if(rx_done)
{
// старт транзации во второй буфер
alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors2[0]);
// пуск пакета N 2 1152 байта из источника (пользовательской логики)
IOWR_ALTERA_AVALON_PUSK(AVSOURCE_0_BASE);
Delay(0x0007);
IOWR_ALTERA_AVALON_STOP(AVSOURCE_0_BASE);
}
else
{
// старт транзации в первый буфер
alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors1[0]);
// пуск пакета N 1 1152 байта из источника (пользовательской логики)
IOWR_ALTERA_AVALON_PUSK(AVSOURCE_0_BASE);
Delay(0x0007);
IOWR_ALTERA_AVALON_STOP(AVSOURCE_0_BASE);
}

// получение результата
for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
{
if(rx_done)
receive_ptr = receive_descriptors1[buffer_counter].write_addr;
else
receive_ptr = receive_descriptors2[buffer_counter].write_addr;
}
for(contents_counter = 0; contents_counter < temp_length; contents_counter++)
{
// массив с результатом
ethmass_ptr[contents_counter + 16] = IORD_8DIRECT((alt_u32)receive_ptr, contents_counter);
... далее выдача по ethenet...
}
}

}

#define NUMBER_OF_BUFFERS 1
#define BUFFER_LENGTH 16
alt_sgdma_descriptor *receive_descriptors1, *receive_descriptors_copy1;
alt_sgdma_descriptor *receive_descriptors2, *receive_descriptors_copy2;
alt_sgdma_descriptor *receive_descriptors_sw, *receive_descriptors_copy_sw;
// если была передача по Ethernet
if(!buff_done)
{
// запуск транзакции в чередной буфер
alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors_sw[0]);
// пуск пакета из пользовательской логики
IOWR_ALTERA_AVALON_PUSK(AVSOURCE_0_BASE);
Delay(0x000f);
IOWR_ALTERA_AVALON_STOP(AVSOURCE_0_BASE);
}
// обработка и посылка пакета из предыдущего буфера
if(buff_done)
{
for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
{
receive_ptr = receive_descriptors_sw[buffer_counter].write_addr;
for(contents_counter = 0; contents_counter < temp_length; contents_counter++)
{
// формирование пакетов COM и Ethernet
chltemp_receive[contents_counter] = 0;
chltemp_receive[contents_counter] = IORD_8DIRECT((alt_u32)receive_ptr, contents_counter);
ethmass_ptr[contents_counter + 16] = chltemp_receive[contents_counter];
}
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, led);
// послать сом и Ethernet пакет
fprintf(fp, chltemp_receive);
eth_ocm_raw_send(ethmass_ptr, sizeof(ethmass_ptr));
}
// пакеты посланы
buff_done = 0;
}

// Обработчик прерываний SGDMA_0_IRQ
static void receive_callback_function(void * context)
{
rx_done++;
if(rx_done > 1) rx_done = 0;
if(rx_done)
{
receive_descriptors_sw = receive_descriptors1;
receive_descriptors_copy_sw = receive_descriptors_copy1;
}
else
{
receive_descriptors_sw = receive_descriptors2;
receive_descriptors_copy_sw = receive_descriptors_copy2;
}

buff_done = 1;
}

// определение подпрограммы обработчика прерываний
  alt_avalon_sgdma_register_callback(receive_DMA,
                                    &receive_callback_function,
                                    (ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK |
                                    ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK),
                                    NULL);

#define NUMBER_OF_BUFFERS 4  
#define BUFFER_LENGTH 16

alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors_sw[0]);

#define NUMBER_OF_BUFFERS 4
#define BUFFER_LENGTH 1152
alt_sgdma_descriptor *receive_descriptors1, *receive_descriptors_copy1;
alt_sgdma_descriptor *receive_descriptors2, *receive_descriptors_copy2;
alt_sgdma_descriptor *receive_descriptors_sw, *receive_descriptors_copy_sw;

alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors_sw[0]);                                                

IOWR_ALTERA_AVALON_PUSK(FIRSOURCE_0_BASE);
Delay(0x0002);
IOWR_ALTERA_AVALON_STOP(FIRSOURCE_0_BASE);
Delay(0x000f);

alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors_sw[0]);

rx_done++;
if(rx_done == 2) rx_done = 0;
if(rx_done)
{
rx_done = 0;
receive_descriptors_sw = receive_descriptors1;
receive_descriptors_copy_sw = receive_descriptors_copy1;
}
else
{
receive_descriptors_sw = receive_descriptors2;
receive_descriptors_copy_sw = receive_descriptors_copy2;
}


for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
{
receive_ptr = receive_descriptors_sw[buffer_counter].write_addr;

// послать Ethernet пакет
ethmass_ptr[15]++;
ethmass_ptr[14] = eth_ocm_raw_send(receive_ptr, 1152);

}

       // старт приема по sgdma

          rx_done = 0;

          receive_descriptors_sw = receive_descriptors1;
          receive_descriptors_copy_sw = receive_descriptors_copy1;

          // чтение регистра управления  
          control = IORD_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_0_BASE);  
          //
          control |= ALTERA_AVALON_SGDMA_CONTROL_PARK_MSK;
          // запись регистра управления
          IOWR_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_0_BASE, control);

          alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors_sw[0]);                                                
          // запуск пакета из пользовательской логики
          IOWR_ALTERA_AVALON_PUSK(FIRSOURCE_0_BASE);
          Delay(0x0002);
          IOWR_ALTERA_AVALON_STOP(FIRSOURCE_0_BASE);
          Delay(0x000f);

  irq_count ++; if(irq_count == 4) irq_count = 0;
  // на последнем прерывании запуск sgdma не делать
  if(irq_count < 4)
    alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors_sw[0]);

  rx_done++;
  if(rx_done == 2) rx_done = 0;
  if(!rx_done)
  {
    receive_descriptors_sw = receive_descriptors1;
    receive_descriptors_copy_sw = receive_descriptors_copy1;
  }
  else
  {
    receive_descriptors_sw = receive_descriptors2;
    receive_descriptors_copy_sw = receive_descriptors_copy2;
  }

  
  for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
  {
    receive_ptr = receive_descriptors_sw[buffer_counter].write_addr;

    // послать Ethernet пакет
    ethmass_ptr[15]++;
     ethmass_ptr[14] = eth_ocm_raw_send(receive_ptr, 1152);

  }

// размещение дескрипторов
return_code = descriptor_allocation(&receive_descriptors1,
&receive_descriptors_copy1,
NUMBER_OF_BUFFERS);
return_code = descriptor_allocation(&receive_descriptors2,
&receive_descriptors_copy2,
NUMBER_OF_BUFFERS);

// создание дескрипторов
return_code = create_test_data(receive_descriptors1,
NUMBER_OF_BUFFERS,
BUFFER_LENGTH);
return_code = create_test_data(receive_descriptors2,
NUMBER_OF_BUFFERS,
BUFFER_LENGTH);

// определение подпрограммы обработчика прерываний
alt_avalon_sgdma_register_callback(receive_DMA,
&receive_callback_function,
(ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK |
ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK),
NULL);

    if(return_code == 1)
    {
        printf("Allocating the data buffers failed... exiting\n");
        return 1;
    }
    else printf("Allocating the data buffers... success\n");

// размещение десрипторов
alt_u32 descriptor_allocation(alt_sgdma_descriptor ** receive_descriptors,
alt_sgdma_descriptor ** receive_descriptors_copy,
alt_u32 number_of_buffers)
{
/* Allocate some big buffers to hold all descriptors which will slide until
* the first 32 byte boundary is found */
void * temp_ptr_2;

/**************************************************************
* Allocation of the receive descriptors *
* - First allocate a large buffer to the temporary pointer *
* - Second check for sucessful memory allocation *
* - Third put this memory location into the pointer copy *
* to be freed before the program exits *
* - Forth slide the tempory pointer until it lies on a 32 *
* byte boundary (descriptor master is 256 bits wide) *
************************************************************/
temp_ptr_2 = malloc((number_of_buffers + 2) * ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE);
if(temp_ptr_2 == NULL)
{
printf("Failed to allocate memory for the receive descriptors\n");
return 1;
}
*receive_descriptors_copy = (alt_sgdma_descriptor *)temp_ptr_2;

while((((alt_u32)temp_ptr_2) % ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE) != 0)
{
temp_ptr_2++; // slide the pointer until 32 byte boundary is found
}
*receive_descriptors = (alt_sgdma_descriptor *)temp_ptr_2;
/**************************************************************/

/* Clear out the null descriptor owned by hardware bit. These locations
* came from the heap so we don't know what state the bytes are in (owned bit could be high).*/
receive_descriptors[number_of_buffers]->control = 0;

return 0; // no failures in allocation
}
//---------------------------------------------------------------------------------------------
/********************************************************************************
**
* This function is responsible for allocating the data buffer for each *
* descriptor. A random buffer length will be generated if you set the minimum *
* and maximum buffer lengths to be different. To run a more controlled test, set *
* the minimum and maximum buffer lengths to be equal. *
* *
* Returns 0 for sucess, 1 for failure. *
********************************************************************************
**/

alt_u32 create_test_data(alt_sgdma_descriptor * receive_descriptors,
alt_u32 number_of_buffers,
alt_u32 buffer_length)
{

alt_u32 buffer_counter, contents_counter, temp_length;
alt_u32 *receive_ptr;
alt_u8 *receive_ptr_copy; // will use these to fill up the tx buffers and clear the rx buffers


/* Initialization of the buffer memories and the transmit+receive descriptors */
for(buffer_counter = 0; buffer_counter < number_of_buffers; buffer_counter++)
{
/* Generate a random buffer length between within MINIMUM_BUFFER_LENGTH and MAXIMUM_BUFFER_LENGTH */
temp_length = buffer_length;

receive_ptr = (alt_u32 *)malloc(temp_length); // since the same contents will be received the length is the same

/* This will populate sequential data (modulo 256) in each transmit buffer a byte at a time.
* The recieve buffers are also cleared with zeros so that each time this software is run
* the data can be reverified. Before this function returns a flush will be performed to
* make sure none of these writes are still in the data cache.
*/
receive_ptr_copy = (alt_u8 *)receive_ptr;

for(contents_counter = 0; contents_counter < temp_length; contents_counter++)
{
receive_ptr_copy[contents_counter] = 0;
}

/* This will create a descriptor that is capable of transmitting data from an Avalon-ST FIFO
* to an Avalon-MM buffer */
alt_avalon_sgdma_construct_stream_to_mem_desc(&receive_descriptors[buffer_counter], // descriptor
&receive_descriptors[buffer_counter+1], // next descriptor
receive_ptr, // write buffer location
(alt_u16)temp_length, // length of the buffer
0); // writes are not to a fixed location

}

alt_dcache_flush_all(); // make sure all the transmit buffers and cleared receive buffers go out to main memory

return 0; // no failures creating data buffers
}

// количество буферов
#define NUMBER_OF_BUFFERS 4
// длина одного буфера
#define BUFFER_LENGTH 1152
// Каждый дескриптор имеет размер в 32 бита
#define ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE (0x20)
void * temp_ptr_2;
// выделение памяти под дескрипторы = 6 * 32 = 192 бита
temp_ptr_2 = malloc((number_of_buffers + 2) * ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE);
// инициализация указателя *receive_descriptors_copy - указывает на адрес начала памяти выделенной под дескрипторы
*receive_descriptors_copy = (alt_sgdma_descriptor *)temp_ptr_2;
// инициализация указателя *receive_descriptors - ???
while((((alt_u32)temp_ptr_2) % ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE) != 0)
{
  temp_ptr_2++;  // slide the pointer until 32 byte boundary is found
}
*receive_descriptors = (alt_sgdma_descriptor *)temp_ptr_2;
// очистка бита OWNED_BY_HW
receive_descriptors[number_of_buffers]->control = 0;

          if (!(IORD_ALTERA_AVALON_SGDMA_STATUS(SGDMA_0_BASE) & ALTERA_AVALON_SGDMA_STATUS_BUSY_MSK))
            IOWR_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_0_BASE, ALTERA_AVALON_SGDMA_CONTROL_PARK_MSK);

          alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors1[0]);

        while (IORD_ALTERA_AVALON_SGDMA_STATUS(SGDMA_0_BASE) & ALTERA_AVALON_SGDMA_STATUS_BUSY_MSK);
        // Enable SGDMA "parking" mode
        if (!(IORD_ALTERA_AVALON_SGDMA_STATUS(SGDMA_0_BASE) & ALTERA_AVALON_SGDMA_STATUS_BUSY_MSK))
          IOWR_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_0_BASE, ALTERA_AVALON_SGDMA_CONTROL_PARK_MSK);

        alt_avalon_sgdma_do_async_transfer(receive_DMA, &receive_descriptors2[0]);
.....
выдача данных из receive_descriptors1 по Ethernet

unsigned char adc_dma_restart(alt_video_display *display)
{
//    while (IORD_ALTERA_AVALON_SGDMA_STATUS(display->sgdma->base) & ALTERA_AVALON_SGDMA_STATUS_BUSY_MSK);
      /* Enable SGDMA "parking" mode */
    if (!(IORD_ALTERA_AVALON_SGDMA_STATUS(display->sgdma->base) & ALTERA_AVALON_SGDMA_STATUS_BUSY_MSK))
    IOWR_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_0_BASE,
        ALTERA_AVALON_SGDMA_CONTROL_PARK_MSK);

      /* Now start the SGDMA */
return(      alt_avalon_sgdma_do_async_transfer(
        display->sgdma,
        display->buffer_ptrs[display->buffer_being_displayed]->desc_base));
}

adc_dma->buffer_being_displayed=dmaindex&0x3;//след. буфер и старт транзакции
  dmaindex++;
  adc_dma_restart(adc_dma);