alt_sgdma_descriptor *receive_descriptors1, *receive_descriptors_copy1;
alt_sgdma_descriptor *receive_descriptors2, *receive_descriptors_copy2;

  for(buffer_counter = 0; buffer_counter < number_of_buffers; buffer_counter++)
  {
  temp_length = buffer_length;
    
  receive_ptr = (alt_u32 *)malloc(temp_length);  
  receive_ptr_copy = (alt_u8 *)receive_ptr;
  
  for(contents_counter = 0; contents_counter < temp_length; contents_counter++)
  {
    receive_ptr_copy[contents_counter] = 0;
  }

  alt_avalon_sgdma_construct_stream_to_mem_desc(
                  &receive_descriptors[buffer_counter],  // descriptor
      &receive_descriptors[buffer_counter+1], // next descriptor
      receive_ptr,  // write buffer location
      (alt_u16)temp_length,  // length of the buffer
      0); // writes are not to a fixed location

  }

alt_sgdma_descriptor *desc = (alt_sgdma_descriptor *) DESCRIPTOR_MEMORY_BASE;
unsigned char* pkt  = MEM_RX_BASE

alt_avalon_sgdma_register_callback(sgdma_rx_dev,(alt_avalon_sgdma_callback)&tse_sgdmaRx_isr,(alt_u16)ALTERA_AVALON_SGDMA_CONTROL_IE_DESC_COMPLETED_MSK | ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK,sgdma_rx_dev);
    alt_u32 *uncached_packet_payload;
    uncached_packet_payload = pkt; //(void *)alt_remap_cached ((volatile void*) pkt, 4);

    alt_avalon_sgdma_construct_stream_to_mem_desc(
            (alt_sgdma_descriptor *) &desc[ALTERA_TSE_FIRST_RX_SGDMA_DESC_OFST],  // descriptor I want to work with
            (alt_sgdma_descriptor *) &desc[ALTERA_TSE_SECOND_RX_SGDMA_DESC_OFST],  // pointer to "next"
            uncached_packet_payload,            // starting write_address
            0,                                  // read until EOP
            0);
   while ( (IORD_ALTERA_AVALON_SGDMA_STATUS(S_SGDMA_RX_BASE) & ALTERA_AVALON_SGDMA_STATUS_BUSY_MSK) );
    uncached_packet_payload = pkt+(256);

alt_avalon_sgdma_construct_stream_to_mem_desc(
        (alt_sgdma_descriptor *) &desc[ALTERA_TSE_SECOND_RX_SGDMA_DESC_OFST],  // descriptor I want to work with
        (alt_sgdma_descriptor *) &desc[ALTERA_TSE_FIRST_RX_SGDMA_DESC_OFST],  // pointer to "next"
        (uncached_packet_payload),            // starting write_address
        0,                                  // read until EOP
        0);

IOWR_ALTERA_AVALON_SGDMA_CONTROL(S_SGDMA_RX_BASE, ALTERA_AVALON_SGDMA_CONTROL_PARK_MSK);

desc[ALTERA_TSE_FIRST_RX_SGDMA_DESC_OFST].control=128; //выставляю OWNED_BY_HW для первого дескриптора

while ( (IORD_ALTERA_AVALON_SGDMA_STATUS(S_SGDMA_RX_BASE) & ALTERA_AVALON_SGDMA_STATUS_BUSY_MSK) );

alt_avalon_sgdma_do_async_transfer(sgdma_rx_dev, &desc[ALTERA_TSE_SECOND_RX_SGDMA_DESC_OFST]);

#define ALTERA_TSE_SGDMA_INTR_MASK              ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK | ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK |
ALTERA_AVALON_SGDMA_CONTROL_IE_EOP_ENCOUNTERED_MSK |
ALTERA_AVALON_SGDMA_CONTROL_IE_ERROR_MSK |
ALTERA_AVALON_SGDMA_CONTROL_IE_DESC_COMPLETED_MSK

if(n_desc==0)
     {
         t2=alt_avalon_sgdma_do_async_transfer(sgdma_rx_dev, &desc[ALTERA_TSE_FIRST_RX_SGDMA_DESC_OFST]);
         n_desc=1;
     }
         else
         {

         alt_avalon_sgdma_do_async_transfer(sgdma_rx_dev, &desc[ALTERA_TSE_SECOND_RX_SGDMA_DESC_OFST]);
          n_desc=0;
         }

alt_avalon_sgdma_do_async_transfer(sgdma_rx_dev, &desc[ALTERA_TSE_SECOND_RX_SGDMA_DESC_OFST]);

IOWR_8DIRECT(&next->control, 0,   (next->control & ~ALTERA_AVALON_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK));

int AD7760_prepare_sgdma()
{
ad7760_sgdma = alt_avalon_sgdma_open(SGDMA_1_NAME);

// check
if( ad7760_sgdma == NULL)
{
//TRACE_STR("--> Failed to open SG_DMA_1 Stream-to-memory!\r\n");
return (-1);
}

alt_avalon_sgdma_register_callback(
ad7760_sgdma,
AD7760_callback,
(ALTERA_AVALON_SGDMA_CONTROL_PARK_MSK |
ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK |
ALTERA_AVALON_SGDMA_CONTROL_IE_MAX_DESC_PROCESSED_MSK |
(8<<ALTERA_AVALON_SGDMA_CONTROL_MAX_DESC_PROCESSED_OFST) ),
NULL);

return 0;
}

void AD7760_prepare_loop_descr_chain()
{
int i;

for( i = 0; i<16; i++ )
{
alt_avalon_sgdma_construct_stream_to_mem_desc(
adchi_desc[i],
(i < 15) ? adchi_desc[i+1] : adchi_desc[0],
(alt_u32*)pFastPacket[i]->data, // Area in external SRAM
FAST_PACKET_BODY_SIZE_BYTES, // in bytes
0 ); // non-fixed write address
}

adchi_desc[0]->control |= ALTERA_AVALON_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK; // Last-first descriptor
}

void AD7760_start_sgdma()
{
alt_avalon_sgdma_do_async_transfer( ad7760_sgdma, adchi_desc[0] );
}

alt_avalon_sgdma_do_async_transfer( ad7760_sgdma, adchi_desc[0] );