//=============================================================================
// GPIOB configuration
//=============================================================================

// enable GPIOB clock
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;

// Alternate Function
GPIOB->MODER = 0; // clear moder register
GPIOB->MODER |=
(
//GPIO_MODER_MODER12_1 | // Alternate Function, SPI2 NSS
GPIO_MODER_MODER13_1 | // Alternate Function, SPI2 SCK
//GPIO_MODER_MODER14_1 | // Alternate Function, SPI2 MISO
GPIO_MODER_MODER15_1 | // Alternate Function, SPI2 MOSI

GPIO_MODER_MODER9_1 | // Alternate Function, I2C1, SDA
GPIO_MODER_MODER8_1 | // Alternate Function, I2C1, SCL

GPIO_MODER_MODER4_1 | // AF, PWM_OUT1, TIM3_CH1
GPIO_MODER_MODER5_1 | // AF, PWM_OUT2, TIM3_CH2
GPIO_MODER_MODER0_1 | // AF, PWM_OUT3, TIM3_CH3
GPIO_MODER_MODER1_1 | // AF, PWM_OUT4, TIM3_CH4
GPIO_MODER_MODER6_1 | // AF, PWM_IN5, TIM4_CH1
GPIO_MODER_MODER7_1 // AF, PWM_IN6, TIM4_CH2
);

// Output type
GPIOB->OTYPER = 0; // clear otype register
GPIOB->OTYPER |= // push-pull if 0
(
GPIO_OTYPER_OT_8 | // Open-Drain, I2C1, SCL
GPIO_OTYPER_OT_9 // OPen-Drain, I2C1, SDA
);

// Speed type
GPIOB->OSPEEDR = 0; // clear ospeedr register
GPIOB->OSPEEDR |=
(
//GPIO_OSPEEDER_OSPEEDR12_1 | // SPI2 NSS 50MH
GPIO_OSPEEDER_OSPEEDR13_1 | // SPI2 SCK, 50MHz
//GPIO_OSPEEDER_OSPEEDR14_1 | // SPI2 MISO 50MH
GPIO_OSPEEDER_OSPEEDR15_1 | // SPI2 MOSI 50MH

GPIO_OSPEEDER_OSPEEDR4_1 | // PWM_OUT1, TIM3_CH1, 50MHz
GPIO_OSPEEDER_OSPEEDR5_1 | // PWM_OUT2, TIM3_CH2, 50MHz
GPIO_OSPEEDER_OSPEEDR0_1 | // PWM_OUT3, TIM3_CH3, 50MHz
GPIO_OSPEEDER_OSPEEDR1_1 | // PWM_OUT4, TIM3_CH4, 50MHz
GPIO_OSPEEDER_OSPEEDR6_1 | // PWM_IN5, TIM4_CH1, 50MHz
GPIO_OSPEEDER_OSPEEDR7_1 // PWM_IN6, TIM4_CH2, 50MHz
);

// Push/Pull
GPIOB->PUPDR = 0; // clear pupdr register
GPIOB->PUPDR |=
(
GPIO_PUPDR_PUPDR8_0 | // Pull-Up, I2C1, SCL
GPIO_PUPDR_PUPDR9_0 | // Pull-Up, I2C1, SDA
GPIO_PUPDR_PUPDR4_0 | // Pull-Up, PWM_OUT1, TIM3_CH1
GPIO_PUPDR_PUPDR5_0 | // Pull-Up, PWM_OUT2, TIM3_CH2
GPIO_PUPDR_PUPDR0_0 | // Pull-Up, PWM_OUT3, TIM3_CH3
GPIO_PUPDR_PUPDR1_0 | // Pull-Up, PWM_OUT4, TIM3_CH4
GPIO_PUPDR_PUPDR6_0 | // Pull-Up, PWM_IN5, TIM4_CH1
GPIO_PUPDR_PUPDR7_0 // Pull-Up, PWM_IN6, TIM4_CH2
);


// Alternate Function pins
GPIOB->AFR[1] = 0; // clear AFR_H register
GPIOB->AFR[1] |=
(
(4 << ((8 - 8) << 2)) | // I2C1 SCL, AF4
(4 << ((9 - 8) << 2)) | // I2C1 SDA, AF4

//(5 << ((12 - 8) << 2)) | // SPI2 NSS, AF5
(5 << ((13 - 8) << 2)) | // SPI2 SCK, AF5
//(5 << ((14 - 8) << 2)) | // SPI2 MISO, AF5
(5 << ((15 - 8) << 2)) // SPI2 MOSI, AF5

);

GPIOB->AFR[0] = 0; // clear AFR_L register
GPIOB->AFR[0] |=
(
(2 << ((4 - 0) << 2)) | // PWM_OUT1, TIM3_CH1, AF2
(2 << ((5 - 0) << 2)) | // PWM_OUT2, TIM3_CH2, AF2
(2 << ((0 - 0) << 2)) | // PWM_OUT3, TIM3_CH3, AF2
(2 << ((1 - 0) << 2)) | // PWM_OUT4, TIM3_CH4, AF2
(2 << ((6 - 0) << 2)) | // TIM4_CH1, AF2
(2 << ((7 - 0) << 2)) // TIM4_CH2, AF2
);

GPIOB->ODR |= GPIO_ODR_ODR_12;

//////////////// SPI2 Communication Routine ///////////////////////////////////
while ( ( (SPI2 -> SR) & SPI_SR_TXE ) == RESET)
{
// wait until TXE bit is 1
}
GPIOB->ODR &= !GPIO_ODR_ODR_12;

SPI2 -> DR = d0;


while ( //( ( (SPI2 -> SR) & SPI_SR_TXE ) == RESET) &&
(( (SPI2 -> SR) & SPI_SR_RXNE ) == RESET) )
{

}

dd = SPI2->DR;


while ( //( ( (SPI2 -> SR) & SPI_SR_TXE ) == RESET) &&
(( (SPI2 -> SR) & SPI_SR_BSY ) == SET) )
{

}


GPIOB->ODR |= GPIO_ODR_ODR_12;