library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comp is
GENERIC(width: INTEGER:=3);
Port ( CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
A, B: in STD_LOGIC_VECTOR(width downto 0);
ALB, AGB: out STD_LOGIC;
ALEB, AGEB: out STD_LOGIC;
AEB, ANEB: out STD_LOGIC );
end comp;

architecture Behavioral of comp is
begin
process(CLK,RESET)
begin
  if (RESET = '1') then
      ALB  <= '0';
      AGB  <= '0';
      ALEB <= '0';
      AGEB <= '0';
      AEB  <= '0';
      ANEB <= '0';
  elsif (CLK'event and CLK ='1') then  
    if ( A < B ) then ALB <= '1';
    else ALB <= '0';
    end if;
  if ( A > B ) then AGB <= '1';
    else AGB <= '0';
    end if;
  if ( A <= B ) then ALEB <= '1';
    else ALEB <= '0';
    end if;
  if ( A >= B ) then AGEB <= '1';
    else AGEB <= '0';
    end if;
  if ( A = B ) then AEB <= '1';
    else AEB <= '0';
    end if;
  if ( A /= B ) then ANEB <= '1';
    else ANEB <= '0';
    end if;  end if;
end process;

end Behavioral;

BEGIN
m1 : for i in 0 to N-1 generate
mul: Dmull port map (
        clk => clk,
        a => std_logic_vector(SumA1a(i)),
        b => std_logic_vector(CoeffDiff(i)),
        p => SumA2V(i));
end generate m1;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.numeric_std.ALL;
use work.FilterPak.all;

ENTITY FilterFormII IS
   PORT( clk                    :   IN    std_logic;
          clken            :   IN    std_logic;
            reset                    :   IN    std_logic;
         filter_in            :   IN    std_logic_vector(POW_IN-1 DOWNTO 0);
         filter_out            :   OUT   std_logic_vector(POW_OUT-1 DOWNTO 0)
         );

END;

ARCHITECTURE rtl OF FilterFormII IS
COMPONENT mult

    PORT
(      aclr        : IN STD_LOGIC;
        clken        : IN STD_LOGIC;    
        clock        : IN STD_LOGIC;
        dataa        : IN signed (9 DOWNTO 0);
        datab        : IN signed (15 DOWNTO 0);
        result    : OUT signed (25 DOWNTO 0)
    );
END COMPONENT;
    TYPE regmul_pipeline_type IS ARRAY (NATURAL range <>) OF signed(POW_IN+POW_COEFF-1 DOWNTO 0);
    TYPE regsum_pipeline_type IS ARRAY (NATURAL range <>) OF signed(POW_SUMM-1 DOWNTO 0);
    TYPE coeff_type IS ARRAY (NATURAL range <>) OF signed(POW_COEFF-1 DOWNTO 0);
    signal reg_mul : regmul_pipeline_type(N_COEFF-1 DOWNTO 0):= (OTHERS => (OTHERS => '0'));
    signal reg_sum : regsum_pipeline_type(FILTER_ORDER+1 DOWNTO 0):= (OTHERS => (OTHERS => '0'));
    signal input : signed(POW_IN-1 DOWNTO 0);


BEGIN

input <= signed(filter_in);


multiple:        for i in 0 to N_COEFF-2 generate
mult_inst: mult port map
         (aclr    => not reset ,
           clken    => clken,
            clock => clk,
            dataa => input,
            datab => coeff(i),
            result => reg_mul(i) );
            
    --        reg_mul(i) <= input * coeff(i);
            reg_sum(i) <= resize(reg_sum(i+1),POW_SUMM) + resize(reg_mul(i),POW_SUMM);
            reg_sum(FILTER_ORDER-i) <= resize(reg_sum(FILTER_ORDER+1-i),POW_SUMM) + resize(reg_mul(i),POW_SUMM);
        end generate;
        
b2v_inst : mult
  PORT MAP(clock => clk,
            clken    => clken,
            aclr    => not reset,
            dataa => input,
            datab => coeff(N_COEFF-1),
            result =>  reg_mul(N_COEFF-1)
         );
        
    --    reg_mul(N_COEFF-1) <= input * coeff(N_COEFF-1);
        reg_sum(N_COEFF-1) <= resize(reg_sum(N_COEFF),POW_SUMM) + resize(reg_mul(N_COEFF-1),POW_SUMM);

filter_out <=std_logic_vector( resize(reg_sum(0)(POW_SUMM-1 DOWNTO POW_POINT),POW_OUT));

END rtl;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
USE IEEE.numeric_std.ALL;

package FilterPak is
    constant POW_IN            : natural := 10;--разрядность входных данных
    constant POW_OUT         : natural := 10;--разрядность выходных данных
    constant POW_COEFF        : natural := 16;--разрядность коэффициентов
    constant POW_SUMM        : natural := 28;--разрядность сумматоров
    constant POW_POINT        : natural := 10;--позиция точки
    constant FILTER_ORDER    : natural := 64; --порядок фильтра чётный(общее число коэффициентов = FILTER_ORDER+1)
    constant N_COEFF         : natural := FILTER_ORDER/2+1;
    TYPE coeff_type IS ARRAY (NATURAL range <>) OF signed(POW_COEFF-1 DOWNTO 0);
    constant coeff             : coeff_type(0 TO N_COEFF-1) := (
to_signed(   -48, POW_COEFF),
to_signed(   -22, POW_COEFF),
to_signed(    80, POW_COEFF),
to_signed(   -22, POW_COEFF),
to_signed(   -98, POW_COEFF),
to_signed(    58, POW_COEFF),
to_signed(   134, POW_COEFF),
to_signed(  -140, POW_COEFF),
to_signed(  -134, POW_COEFF),
to_signed(   244, POW_COEFF),
to_signed(    98, POW_COEFF),
to_signed(  -370, POW_COEFF),
to_signed(     2, POW_COEFF),
to_signed(   494, POW_COEFF),
to_signed(  -180, POW_COEFF),
to_signed(  -588, POW_COEFF),
to_signed(   446, POW_COEFF),
to_signed(   610, POW_COEFF),
to_signed(  -800, POW_COEFF),
to_signed(  -510, POW_COEFF),
to_signed(  1228, POW_COEFF),
to_signed(   228, POW_COEFF),
to_signed( -1698, POW_COEFF),
to_signed(   310, POW_COEFF),
to_signed(  2176, POW_COEFF),
to_signed( -1226, POW_COEFF),
to_signed( -2612, POW_COEFF),
to_signed(  2806, POW_COEFF),
to_signed(  2966, POW_COEFF),
to_signed( -6086, POW_COEFF),
to_signed( -3194, POW_COEFF),
to_signed( 20562, POW_COEFF),
to_signed( 36042, POW_COEFF)

);
end package FilterPak;