#
NET "e0rx_clk" PERIOD = 40 ns;
OFFSET = IN 10 ns BEFORE "e0rx_clk";
NET "e0tx_clk" PERIOD = 40 ns;
OFFSET = OUT 20 ns AFTER "e0tx_clk";
OFFSET = IN 10 ns BEFORE "e0tx_clk";

NET "e0rx_clk" TNM_NET = "e0rx_clk";
NET "e0tx_clk" TNM_NET = "e0tx_clk";

TIMESPEC TS_erxclk = PERIOD "e0rx_clk" 36 ns;
TIMESPEC TS_etxclk = PERIOD "e0tx_clk" 36 ns;
#
OFFSET = IN 8 ns VALID 15 ns BEFORE "e0rx_clk";
OFFSET = OUT 15 ns AFTER "e0tx_clk";

# place a constraint on the LAN tx signals timing
NET "e0tx_clk" TNM = "LAN_TX_OUT";
#NET "TX_CTL" TNM = "LAN_TX_OUT";
NET "e0tx_en" TNM = "LAN_TX_OUT";
NET "e0tx_er" TNM = "LAN_TX_OUT";
NET "e0txd[0]" TNM = "LAN_TX_OUT";
NET "e0txd[1]" TNM = "LAN_TX_OUT";
NET "e0txd[2]" TNM = "LAN_TX_OUT";
NET "e0txd[3]" TNM = "LAN_TX_OUT";
NET "e0txd[4]" TNM = "LAN_TX_OUT";
NET "e0txd[5]" TNM = "LAN_TX_OUT";
NET "e0txd[6]" TNM = "LAN_TX_OUT";
NET "e0txd[7]" TNM = "LAN_TX_OUT";

TIMEGRP "LAN_TX_OUT" OFFSET = OUT 10.5 ns AFTER "e0rx_clk";

# In addition, place a constraint on the input pins from the PHY to minimize the delay spread among the rx pins
# place a constraint on the LAN rx signals timing
#NET "RX_CTL" TNM = "LAN_RX_IN";
NET "e0rx_er" TNM = "LAN_RX_IN";
NET "e0rxd[0]" TNM = "LAN_RX_IN";
NET "e0rxd[1]" TNM = "LAN_RX_IN";
NET "e0rxd[2]" TNM = "LAN_RX_IN";
NET "e0rxd[3]" TNM = "LAN_RX_IN";
NET "e0rxd[4]" TNM = "LAN_RX_IN";
NET "e0rxd[5]" TNM = "LAN_RX_IN";
NET "e0rxd[6]" TNM = "LAN_RX_IN";
NET "e0rxd[7]" TNM = "LAN_RX_IN";

TIMEGRP "LAN_RX_IN" OFFSET = IN 0.5 ns BEFORE "e0rx_clk";

Paths for end point e0txd<6> (V30.PAD), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths): -3.001ns (requirement - (clock arrival + clock path + data path + uncertainty))
Source: e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/TXD_6 (FF)
Destination: e0txd<6> (PAD)
Source Clock: e0/Inst_Top_level_TCP/Inst_COM5401/TX_CLKG rising at 0.000ns
Requirement: 10.500ns
Data Path Delay: 4.111ns (Levels of Logic = 1)
Clock Path Delay: 9.365ns (Levels of Logic = 4)
Clock Uncertainty: 0.025ns

Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns

Maximum Clock Path at Slow Process Corner: e0rx_clk to e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/TXD_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
W27.I Tiopi 1.557 e0rx_clk
e0rx_clk
clk_pad1/xcv2.u0/g0.ttl0.ip
ProtoComp1105.IMUX.23
BUFIO2_X4Y18.I net (fanout=1) 0.627 e0rx_clk_signal
BUFIO2_X4Y18.DIVCLK Tbufcko_DIVCLK 0.190 e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/BUFIO2_inst
e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/BUFIO2_inst
BUFGMUX_X2Y3.I0 net (fanout=1) 1.327 e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/RX_CLK2
BUFGMUX_X2Y3.O Tgi0o 0.209 e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/BUFG_001
e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/BUFG_001
BUFGMUX_X3Y5.I1 net (fanout=62) 2.826 e0/Inst_Top_level_TCP/Inst_COM5401/RX_CLKG
BUFGMUX_X3Y5.O Tgi1o 0.209 e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/BUFGMUX_inst
e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/BUFGMUX_inst
OLOGIC_X35Y94.CLK0 net (fanout=85) 2.420 e0/Inst_Top_level_TCP/Inst_COM5401/TX_CLKG
------------------------------------------------- ---------------------------
Total 9.365ns (2.165ns logic, 7.200ns route)
(23.1% logic, 76.9% route)

Maximum Data Path at Slow Process Corner: e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/TXD_6 to e0txd<6>
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
OLOGIC_X35Y94.OQ Tockq 1.080 e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/TXD<6>
e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/TXD_6
V30.O net (fanout=1) 0.309 e0/Inst_Top_level_TCP/Inst_COM5401/IF_SEL_002.Inst_GMII_MII_WRAPPER/TXD<6>
V30.PAD Tioop 2.722 e0txd<6>
e0txd_6_OBUF
e0txd<6>
------------------------------------------------- ---------------------------
Total 4.111ns (3.802ns logic, 0.309ns route)
(92.5% logic, 7.5% route)

--------------------------------------------------------------------------------

-- two cases: @1000 Mbps (GMII), the GTX_CLK is an output . At 10/100Mbps (MII), the TX_CLK in an input.

-- In the 1000Mbps mode, we must provide a 125 MHz GTX_CLK to the PHY. Make tx clock <= rx clock frequency.
-- In the 10/100 Mbps mode, the TX_CLKG clock is generated by the PHY (may drift w.r.t rx clock frequency)
-- IMPORTANT Key design assumption: PHY always generates a RX_CLK, even when no cable is connected.

BUFGMUX_inst : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchless ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => TX_CLKG, -- 1-bit output: Clock buffer output
I0 => TX_CLK, -- 1-bit input: Clock buffer input (S=0)
I1 => RX_CLKG, -- 1-bit input: Clock buffer input (S=1)
S => GMII_FLAG -- 1-bit input: Clock buffer select
);

BUFIO2_inst : BUFIO2
generic map (
DIVIDE => 1, -- DIVCLK divider (1-8)
DIVIDE_BYPASS => TRUE, -- Bypass the divider circuitry (TRUE/FALSE)
I_INVERT => FALSE, -- Invert clock (TRUE/FALSE)
USE_DOUBLER => FALSE -- Use doubler circuitry (TRUE/FALSE)
)
port map (
DIVCLK => RX_CLK2, -- 1-bit output Divided clock output
IOCLK => open, -- 1-bit output I/O output clock
SERDESSTROBE => open, -- 1-bit output Output SERDES strobe (connect to ISERDES2/OSERDES2)
I => RX_CLK -- 1-bit input Clock input (connect to IBUFG)
);

-- declare the RX clock as a global clock
BUFG_001 : BUFG port map (
O => RX_CLKG, -- Clock buffer output
I => RX_CLK2 -- Clock buffer input
);

RX_CLKG <= RX_CLK;
TX_CLKG <= RX_CLKG;