NET "rgmii_rx_clk0" TNM_NET = "phy_clk_rx0";
TIMESPEC TS_phy_rx0 = PERIOD "phy_rx0" 8 ns HIGH 50 %;
///////////////////////////////////////////////////////
INST "rgmii_rxd0[0]" TNM = "rgmii_rx_d0_0";
INST "rgmii_rxd0[1]" TNM = "rgmii_rx_d0_1";
INST "rgmii_rxd0[2]" TNM = "rgmii_rx_d0_2";
INST "rgmii_rxd0[3]" TNM = "rgmii_rx_d0_3";
INST "rgmii_rx_ctl0" TNM = "rgmii_rx_ctrl0";
///////////////////////////////////////////////////////
TIMEGRP "rgmii_rx_d0_0" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" RISING;
TIMEGRP "rgmii_rx_d0_0" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" FALLING;

TIMEGRP "rgmii_rx_d0_1" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" RISING;
TIMEGRP "rgmii_rx_d0_1" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" FALLING;

TIMEGRP "rgmii_rx_d0_2" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" RISING;
TIMEGRP "rgmii_rx_d0_2" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" FALLING;

TIMEGRP "rgmii_rx_d0_3" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" RISING;
TIMEGRP "rgmii_rx_d0_3" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" FALLING;

TIMEGRP "rgmii_rx_ctrl0" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" RISING;
TIMEGRP "rgmii_rx_ctrl0" OFFSET = IN 0 ns VALID 3.5 ns BEFORE "rgmii_rx_clk0" FALLING;

   (* IODELAY_GROUP = "group_1_0" *) // Specifies group name for associated IODELAYs and IDELAYCTRL
   IODELAY # (
      .DELAY_SRC("I"),  // Specify which input port to be used, "I"=IDATAIN,
                        //  "O"=ODATAIN, "DATAIN"=DATAIN, "IO"=Bi-directional
      .HIGH_PERFORMANCE_MODE("TRUE"), // "TRUE" specifies lower jitter
                                      //   at expense of more power
      .IDELAY_TYPE("FIXED"),  // "FIXED" or "VARIABLE"
      .IDELAY_VALUE(15),         // 0 to 63 tap values
      .ODELAY_VALUE(0),         // 0 to 63 tap values
      .REFCLK_FREQUENCY(200.0), // Frequency used for IDELAYCTRL
                                //   175.0 to 225.0
      .SIGNAL_PATTERN("DATA")  // Input signal type, "CLOCK" or "DATA"
   ) IODELAY_D0 (
      .DATAOUT(rgmii_rxd_delay[0]),   // 1-bit delayed data output
      .C(1'b0),     // 1-bit clock input
      .CE(1'b0),   // 1-bit clock enable input
      .DATAIN(1'b0),     // 1-bit internal data input
      .IDATAIN(rgmii_rxd[0]),   // 1-bit input data input (connect to port)
      .INC(1'b0), // 1-bit increment/decrement input
      .ODATAIN(),   // 1-bit output data input
      .RST(1'b0), // 1-bit active high, synch reset input
      .T(1'b0)      // 1-bit 3-state control input
   );

Slack (setup path):     0.987ns (requirement - (data path - clock path - clock arrival + uncertainty))
   Source:               rgmii_rxd0<0> (PAD)
   Destination:          RGMII_test/rgmii_0/IDDR_0 (FF)
   Destination Clock:    RGMII_test/rgmii_0/clk_out_iodelay rising at 0.000ns
   Requirement:          0.000ns
   Data Path Delay:      2.939ns (Levels of Logic = 2)
   Clock Path Delay:     3.951ns (Levels of Logic = 3)
   Clock Uncertainty:    0.025ns

RX_CLKG <= RX_CLK;
TX_CLKG <= RX_CLK;