library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Count16 is
port(
    clk, rst, ena,up:in std_logic;
    Dout:out std_logic_vector(15 downto 0);
    carry:out std_logic    
    );
end entity;

architecture cn of count16 is

begin
process(clk)
variable cnt_v:unsigned(16 downto 0);
variable car_v:std_logic;
constant zero:unsigned(16 downto 0):="00000000000000000";
constant step:unsigned(16 downto 0):="00000000000000001";
constant max:unsigned(16 downto 0):="10000000000000000";
variable up_v:std_logic_vector(2 downto 0);
begin
    if(rising_edge(clk))then
        up_v:=up_v(1 downto 0)&up;--shift for detect rising edge
        if(rst='1')then
            cnt_v:=zero;
            car_v:='0';
            up_v:="000";
        else
            if(ena='1')then
                if(car_v='0')then
                    if(up_v="011")then
                        cnt_v:=cnt_v+step;
                        if(cnt_v>=max)then
                            car_v:='1';
                        else
                            car_v:='0';
                        end if;
                    end if;
                end if;
            end if;
        end if;
        Dout<=std_logic_vector(cnt_v(15 downto 0));
        carry<=car_v;
    end if;
end process;

end cn;

ххх: process(clk, rst)
     begin
       if(rst = '0') then
         <бла-бла-бла>  -- Асинхронный сброс
       elsif(clk'event and clk = '1') then
         <тыры-пыры>    -- Собственно необходимые действия

       end if;
     end process xxx;