long_code_here =
library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
entity Accumulator is
port (
clk : in std_logic;
rst : in std_logic;
wr : in std_logic;
D : in std_logic_vector (39 downto 0);
S : out std_logic_vector (39 downto 0)
);
end Accumulator;
architecture rtl of Accumulator is
component Adder_4bit is
port (
clk : in std_logic;
rst : in std_logic;
A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
cin : in std_logic;
S : out std_logic_vector (3 downto 0);
cout : out std_logic
);
end component;
component my_reg is
generic (
size : integer range 1 to 255:=1;
W : integer range 1 to 32:=4
);
port (
clk : in std_logic;
rst : in std_logic;
wr : in std_logic;
D : in std_logic_vector (W-1 downto 0);
Q : out std_logic_vector (W-1 downto 0)
);
end component;
type result_type is array(9 downto 0) of std_logic_vector(3 downto 0);
signal res0, res1, res, input : result_type:=(others=>(others=>'0'));
signal carry_chain0, carry_chain1, carry_chain : std_logic_vector (9 downto 0):=(others=>'0');
begin
inputs : for i in 1 to 10 generate
reg_chain : my_reg
generic map (i, 4)
port map (clk, rst, D(4*i-1 downto 4*(i-1)), input(i-1));
end generate;

first_adder : Adder_4bit
port map (clk, rst, input(0), res(0), '0', res(0), carry_chain(0));
adders : for i in 1 to 9 generate
carry : Adder_4bit
port map (clk, rst, input(i), res(i), '1', res1(i), carry_chain1(i));
no_carry : Adder_4bit
port map (clk, rst, input(i), res(i), '0', res0(i), carry_chain0(i));
end generate;
sum_mux : for i in 1 to 9 generate
res(i)<=
res0(i) when carry_chain(i-1)='0' else
res1(i);
carry_chain(i)<=
carry_chain0(i) when carry_chain(i-1)='0' else
carry_chain1(i);
end generate;
output_assign : for i in 1 to 10 generate
S(4*i-1 downto 4*(i-1))<=res(i-1);
end generate;
end rtl;

long_code_here =
library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;

entity Adder_4bit is
port (
clk : in std_logic;
rst : in std_logic;
A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
cin : in std_logic;
S : out std_logic_vector (3 downto 0);
cout : out std_logic
);
end Adder_4bit;

architecture rtl of Adder_4bit is
signal sum : std_logic_vector (4 downto 0);
signal op1, op2 : std_logic_vector (3 downto 0);
begin
process (rst,clk)
begin
if (rst='1') then
sum<=(others=>'0');
elsif (clk'event and clk='1') then
sum <= ('0' & A)+('0' & B )+cin;
end if;
end process;
S <= sum(3 downto 0);
cout <= sum(4);
end rtl;

long_code_here =
library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;

entity my_reg is
generic (
size : integer range 1 to 255:=1;
W : integer range 1 to 32:=4
);
port (
-- Системный интерфейс
clk : in std_logic;
rst : in std_logic;
wr : in std_logic;
D : in std_logic_vector (W-1 downto 0);
Q : out std_logic_vector (W-1 downto 0)
);
end my_reg;

architecture rtl of my_reg is
type reg_chain_type is array (size-1 downto 0) of std_logic_vector (W-1 downto 0);
signal reg_chain : reg_chain_type;
signal ena_chain : std_logic_vector (size-1 downto 0);
begin
process (clk, rst)
begin
if (rst='1') then
ena_chain<=(others=>'0');
elsif (clk'event and clk='1') then
ena_chain(0)<='1';
if (size>1) then
for i in 1 to size-1 loop
ena_chain(i)<=ena_chain(i-1);
end loop;
end if;
end if;
end process;

process (rst, clk)
begin
if (rst='1') then
reg_chain<=(others=>(others=>'0'));
elsif (clk'event and clk='1') then
if (ena_chain(0)='1') then
reg_chain(0)<=D;
end if;
if (size>1) then
for i in 1 to size-1 loop
if (ena_chain(i)='1') then
reg_chain(i)<=reg_chain(i-1);
end if;
end loop;
end if;
end if;
end process;
Q<=reg_chain(size-1);
end rtl;

library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;

entity Sin_func is
port(
clk : in std_logic;
rst : in std_logic;
Din : in std_logic_vector(9 downto 0); -- входные данные. это 10 страших разрядов с выхода накопительного сумматора.
Sout : out std_logic_vector (11 downto 0) -- выходные данные. Значения идут на цап. (амплитуда синуса)
);
end Sin_func;

architecture rtl of Sin_func is
type sin_type is array(31 downto 0) of std_logic_vector(11 downto 0);
signal Reg : sin_type;
signal In_reg : std_logic_vector (9 downto 0);
begin
table0: process(clk, rst)
begin
if (rst='1') then
Reg(0) <= (others=>'0');
elsif(clk'event and clk='1') then
case Din(4 downto 0) is
when "00000" => Reg(0) <= "011111111111";
when "00001" => Reg(0) <= "100000001011";
when "00010" => Reg(0) <= "100000011000";
when "00011" => Reg(0) <= "100000100100";
when "00100" => Reg(0) <= "100000110001";
when "00101" => Reg(0) <= "100000111101";
when "00110" => Reg(0) <= "100001001010";
when "00111" => Reg(0) <= "100001010110";
when "01000" => Reg(0) <= "100001100011";
when "01001" => Reg(0) <= "100001110000";
when "01010" => Reg(0) <= "100001111100";
when "01011" => Reg(0) <= "100010001001";
when "01100" => Reg(0) <= "100010010101";
when "01101" => Reg(0) <= "100010100010";
when "01110" => Reg(0) <= "100010101110";
when "01111" => Reg(0) <= "100010111011";
when "10000" => Reg(0) <= "100011000111";
when "10001" => Reg(0) <= "100011010100";
when "10010" => Reg(0) <= "100011100000";
when "10011" => Reg(0) <= "100011101101";
when "10100" => Reg(0) <= "100011111001";
when "10101" => Reg(0) <= "100100000110";
when "10110" => Reg(0) <= "100100010010";
when "10111" => Reg(0) <= "100100011111";
when "11000" => Reg(0) <= "100100101011";
when "11001" => Reg(0) <= "100100111000";
when "11010" => Reg(0) <= "100101000100";
when "11011" => Reg(0) <= "100101010000";
when "11100" => Reg(0) <= "100101011101";
when "11101" => Reg(0) <= "100101101001";
when "11110" => Reg(0) <= "100101110110";
when "11111" => Reg(0) <= "100110000010";
when others => Reg(0) <= "000000000000";
end case;
end if;
end process;
table1: process(clk, rst)
begin
if (rst='1') then
Reg(1) <= (others=>'0');
elsif(clk'event and clk='1') then
case Din(4 downto 0) is
when "00000" => Reg(1) <= "100110001110";
when "00001" => Reg(1) <= "100110011011";
when "00010" => Reg(1) <= "100110100111";
и так далее... всего 32 таких таблицы.

process(clk, rst)
begin
if (rst='1') then
In_reg <= (others=>'0');
elsif (clk'event and clk='1')then
In_reg <= Din;
end if;
end process;
Sout <= Reg (conv_integer(In_reg(9 downto 5)));
end architecture rtl;

.....

signal Din_1 : std_logic_vector (9 downto 0);

.....

Din_1 <= Din(9 downto 0) when (Din(10) = '0') else "1111111111" - Din(9 downto 0);

table0: process(clk, rst)
begin
    if (rst='1') then
        Reg(0) <= (others=>'0');
    elsif(clk'event and clk='1') then
        case Din_1(4 downto 0) is
            when "00000" => Reg(0) <= "000000000000";
            when "00001" => Reg(0) <= "000000001010";
.....

process(clk, rst)
begin
    if (rst='1') then
        In_reg <= (others=>'0');
    elsif (clk'event and clk='1')then
        In_reg(11 downto 10) <= Din;
        In_reg(9 downto 0) <= Din_1;
    end if;
end process;
    Sout <= "111111111111" + Reg (conv_integer(In_reg(9 downto 5))) when (In_reg(11) = '0'); else "111111111111" - Reg (conv_integer(In_reg(9 downto 5)));

In_reg(11 downto 10) <= Din(11 downto 10);
In_reg(9 downto 0) <= Din_1;

Sout <= "111111111111" + Reg (conv_integer(In_reg(9 downto 5))) when (In_reg(11) = '0'); else "111111111111" - Reg (conv_integer(In_reg(9 downto 5)));