Среди поисков алгоритмов dds нашел вот такой код.
Из этого кода все, что я понял, так это то, что 40 рязрядный сумматор разбит на десять 4-х разрядных сумматоров. Не могли бы Вы описать более подробную картину, что здесь происходит?)
CODE
long_code_here =
library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
entity Accumulator is
port (
clk : in std_logic;
rst : in std_logic;
wr : in std_logic;
D : in std_logic_vector (39 downto 0);
S : out std_logic_vector (39 downto 0)
);
end Accumulator;
architecture rtl of Accumulator is
component Adder_4bit is
port (
clk : in std_logic;
rst : in std_logic;
A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
cin : in std_logic;
S : out std_logic_vector (3 downto 0);
cout : out std_logic
);
end component;
component my_reg is
generic (
size : integer range 1 to 255:=1;
W : integer range 1 to 32:=4
);
port (
clk : in std_logic;
rst : in std_logic;
wr : in std_logic;
D : in std_logic_vector (W-1 downto 0);
Q : out std_logic_vector (W-1 downto 0)
);
end component;
type result_type is array(9 downto 0) of std_logic_vector(3 downto 0);
signal res0, res1, res, input : result_type:=(others=>(others=>'0'));
signal carry_chain0, carry_chain1, carry_chain : std_logic_vector (9 downto 0):=(others=>'0');
begin
inputs : for i in 1 to 10 generate
reg_chain : my_reg
generic map (i, 4)
port map (clk, rst, D(4*i-1 downto 4*(i-1)), input(i-1));
end generate;
first_adder : Adder_4bit
port map (clk, rst, input(0), res(0), '0', res(0), carry_chain(0));
adders : for i in 1 to 9 generate
carry : Adder_4bit
port map (clk, rst, input(i), res(i), '1', res1(i), carry_chain1(i));
no_carry : Adder_4bit
port map (clk, rst, input(i), res(i), '0', res0(i), carry_chain0(i));
end generate;
sum_mux : for i in 1 to 9 generate
res(i)<=
res0(i) when carry_chain(i-1)='0' else
res1(i);
carry_chain(i)<=
carry_chain0(i) when carry_chain(i-1)='0' else
carry_chain1(i);
end generate;
output_assign : for i in 1 to 10 generate
S(4*i-1 downto 4*(i-1))<=res(i-1);
end generate;
end rtl;
library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
entity Accumulator is
port (
clk : in std_logic;
rst : in std_logic;
wr : in std_logic;
D : in std_logic_vector (39 downto 0);
S : out std_logic_vector (39 downto 0)
);
end Accumulator;
architecture rtl of Accumulator is
component Adder_4bit is
port (
clk : in std_logic;
rst : in std_logic;
A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
cin : in std_logic;
S : out std_logic_vector (3 downto 0);
cout : out std_logic
);
end component;
component my_reg is
generic (
size : integer range 1 to 255:=1;
W : integer range 1 to 32:=4
);
port (
clk : in std_logic;
rst : in std_logic;
wr : in std_logic;
D : in std_logic_vector (W-1 downto 0);
Q : out std_logic_vector (W-1 downto 0)
);
end component;
type result_type is array(9 downto 0) of std_logic_vector(3 downto 0);
signal res0, res1, res, input : result_type:=(others=>(others=>'0'));
signal carry_chain0, carry_chain1, carry_chain : std_logic_vector (9 downto 0):=(others=>'0');
begin
inputs : for i in 1 to 10 generate
reg_chain : my_reg
generic map (i, 4)
port map (clk, rst, D(4*i-1 downto 4*(i-1)), input(i-1));
end generate;
first_adder : Adder_4bit
port map (clk, rst, input(0), res(0), '0', res(0), carry_chain(0));
adders : for i in 1 to 9 generate
carry : Adder_4bit
port map (clk, rst, input(i), res(i), '1', res1(i), carry_chain1(i));
no_carry : Adder_4bit
port map (clk, rst, input(i), res(i), '0', res0(i), carry_chain0(i));
end generate;
sum_mux : for i in 1 to 9 generate
res(i)<=
res0(i) when carry_chain(i-1)='0' else
res1(i);
carry_chain(i)<=
carry_chain0(i) when carry_chain(i-1)='0' else
carry_chain1(i);
end generate;
output_assign : for i in 1 to 10 generate
S(4*i-1 downto 4*(i-1))<=res(i-1);
end generate;
end rtl;
Далее идет описание компонента Adder_4bit
CODE
long_code_here =
library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
entity Adder_4bit is
port (
clk : in std_logic;
rst : in std_logic;
A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
cin : in std_logic;
S : out std_logic_vector (3 downto 0);
cout : out std_logic
);
end Adder_4bit;
architecture rtl of Adder_4bit is
signal sum : std_logic_vector (4 downto 0);
signal op1, op2 : std_logic_vector (3 downto 0);
begin
process (rst,clk)
begin
if (rst='1') then
sum<=(others=>'0');
elsif (clk'event and clk='1') then
sum <= ('0' & A)+('0' & B )+cin;
end if;
end process;
S <= sum(3 downto 0);
cout <= sum(4);
end rtl;
library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
entity Adder_4bit is
port (
clk : in std_logic;
rst : in std_logic;
A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
cin : in std_logic;
S : out std_logic_vector (3 downto 0);
cout : out std_logic
);
end Adder_4bit;
architecture rtl of Adder_4bit is
signal sum : std_logic_vector (4 downto 0);
signal op1, op2 : std_logic_vector (3 downto 0);
begin
process (rst,clk)
begin
if (rst='1') then
sum<=(others=>'0');
elsif (clk'event and clk='1') then
sum <= ('0' & A)+('0' & B )+cin;
end if;
end process;
S <= sum(3 downto 0);
cout <= sum(4);
end rtl;
И компонента my_reg
CODE
long_code_here =
library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
entity my_reg is
generic (
size : integer range 1 to 255:=1;
W : integer range 1 to 32:=4
);
port (
-- Системный интерфейс
clk : in std_logic;
rst : in std_logic;
wr : in std_logic;
D : in std_logic_vector (W-1 downto 0);
Q : out std_logic_vector (W-1 downto 0)
);
end my_reg;
architecture rtl of my_reg is
type reg_chain_type is array (size-1 downto 0) of std_logic_vector (W-1 downto 0);
signal reg_chain : reg_chain_type;
signal ena_chain : std_logic_vector (size-1 downto 0);
begin
process (clk, rst)
begin
if (rst='1') then
ena_chain<=(others=>'0');
elsif (clk'event and clk='1') then
ena_chain(0)<='1';
if (size>1) then
for i in 1 to size-1 loop
ena_chain(i)<=ena_chain(i-1);
end loop;
end if;
end if;
end process;
process (rst, clk)
begin
if (rst='1') then
reg_chain<=(others=>(others=>'0'));
elsif (clk'event and clk='1') then
if (ena_chain(0)='1') then
reg_chain(0)<=D;
end if;
if (size>1) then
for i in 1 to size-1 loop
if (ena_chain(i)='1') then
reg_chain(i)<=reg_chain(i-1);
end if;
end loop;
end if;
end if;
end process;
Q<=reg_chain(size-1);
end rtl;
library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
entity my_reg is
generic (
size : integer range 1 to 255:=1;
W : integer range 1 to 32:=4
);
port (
-- Системный интерфейс
clk : in std_logic;
rst : in std_logic;
wr : in std_logic;
D : in std_logic_vector (W-1 downto 0);
Q : out std_logic_vector (W-1 downto 0)
);
end my_reg;
architecture rtl of my_reg is
type reg_chain_type is array (size-1 downto 0) of std_logic_vector (W-1 downto 0);
signal reg_chain : reg_chain_type;
signal ena_chain : std_logic_vector (size-1 downto 0);
begin
process (clk, rst)
begin
if (rst='1') then
ena_chain<=(others=>'0');
elsif (clk'event and clk='1') then
ena_chain(0)<='1';
if (size>1) then
for i in 1 to size-1 loop
ena_chain(i)<=ena_chain(i-1);
end loop;
end if;
end if;
end process;
process (rst, clk)
begin
if (rst='1') then
reg_chain<=(others=>(others=>'0'));
elsif (clk'event and clk='1') then
if (ena_chain(0)='1') then
reg_chain(0)<=D;
end if;
if (size>1) then
for i in 1 to size-1 loop
if (ena_chain(i)='1') then
reg_chain(i)<=reg_chain(i-1);
end if;
end loop;
end if;
end if;
end process;
Q<=reg_chain(size-1);
end rtl;
Здесь, в таких тонкостях, еще хуже. … не понятно, как это функционирует все вместе…
Подскажите, поделитесь своими мыслями!)
Хочу разобраться для начала с этим, поскольку дальше еще используется перекодировка с таблицей синусов.
Заранее большое спасибо всем откликнувшимся!)
).