#*******************************************************************************
## SDC file "HighSpeed.sdc"
## author ViKo
# Формат времени #
set_time_format -unit ns -decimal_places 3
# Входные такты #
create_clock -name ClkIn -period 500MHz -waveform {0 1} {Clk}
# Сигнал дискретизации #
# Определить такты с ФАПЧ #
derive_pll_clocks -create_base_clocks
# Определить нестабильность тактов #
derive_clock_uncertainty
# Задержка входных данных #
set_input_delay -clock ClkIn 0.55 [get_ports {DP[*]A DP[*]B}]
# Задержка выходных данных #
# set_output_delay -clock ClkOut -2 [get_ports {D*}]
set_output_delay -clock ClkOut -min 0 [get_ports {D*}]
set_output_delay -clock ClkOut -max 0 [get_ports {D*}]
# Не проверять путь #
# set_false_path -from ClkOut -to [get_ports {D*}]
# set_multicycle_path -from ClkOut -to D* -start 2
# set_multicycle_path -from ClkOut -to D* -hold 0

`define VERSION1
// `define WID 8

module HighSpeed (
(* altera_attribute = "-name io_standard lvds; -name pad_to_input_register_delay 0", useioff = 1 *)
input bit Clk,
(* altera_attribute = "-name io_standard lvds; -name pad_to_input_register_delay 0", useioff = 1 *)
input bit ClkIn,
(* altera_attribute = "-name io_standard lvds; -name pad_to_input_register_delay 0", useioff = 1 *)
input bit DP1A, DP1B, DP2A, DP2B, DP3A, DP3B, DP4A, DP4B,
(* altera_attribute = "-name io_standard \"2.5 V\"" *)
output bit [31 : 0] D,
(* altera_attribute = "-name io_standard \"2.5 V\"" *)
output bit ClkOut
);

`ifdef VERSION1

AltLvdsRx_mf AltLvdsRx (
.rx_in ({ DP4B, DP4A, DP3B, DP3A, DP2B, DP2A, DP1B, DP1A }),
.rx_inclock (ClkIn),
.rx_out (D),
.rx_outclock (ClkOut)
);

`endif

`ifdef VERSION2

AltLvdsRx1_mf Rx (
.rx_in (DP1A),
.rx_inclock (ClkIn),
.rx_out (D),
.rx_outclock (ClkOut)
);

`endif

endmodule : HighSpeed