library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity LED is
port( CLK : in std_logic;
L_D : out std_logic_vector(3 downto 0)); -- поправил у меня 4 светодиода подключены
end LED;

architecture A_LED of LED is
signal counter : std_logic_vector(20 downto 0):= (others => '0');
signal LED_temp : std_logic_vector(3 downto 0) := (0 => '1',others =>'0'); -- поправил на 4 светодиода
signal res : std_logic := '0';
begin
count : process(CLK,res)
begin
if(res = '1') then
counter <= (others => '0');
elsif(rising_edge(CLK)) then
counter <= counter +1;
end if;
end process;

L : process(counter)
begin
if(counter = 2000000) then
res <= '1';
LED_temp <= LED_temp(2 downto 0) & LED_temp(3);
-- вращаю выходной вектор по кругу налево, постоянно смещая на 1 разряд
else
res <= '0';
end if;
end process;

L_D <= led_temp; -- выдаю информацию из регистров в порт

end A_LED;

signal counter : std_logic_vector(22 downto 0):= (others => '0');
signal LED_temp : std_logic_vector(3 downto 0) := (0 => '1',others =>'0');
signal res : std_logic := '0';
signal phase : std_logic;
begin
  count : process(CLK,res)
  begin
    if(res = '1') then
      counter <= (others => '0');
    elsif(rising_edge(CLK)) then
      counter <= (counter + 1);
    end if;
  end process;
L : process(counter)
  begin
    if(counter = 5000000) then
      res <= '1';
    LED_temp <= LED_temp(2 downto 0) & LED_temp(3);
    phase <= not(phase);
   else
      res <= '0';
    end if;
  end process;
  
G: process (phase)
begin
if (phase = '0') then
L_D <= (others => '0');
else
L_D <= LED_temp;
end if;
end process;

L_D <= led_temp; --  сигнал из регистров в порт
end A_LED;

signal res      : std_logic                     := '0';
signal phase    : std_logic                     := '0';
signal LED_temp : std_logic_vector( 3 downto 0) := (0 => '1', others =>'0');
signal counter  : std_logic_vector(22 downto 0) := (others => '0');

begin
  count : process(CLK, res)
  begin
    if(res = '1') then
      counter <= (others => '0');
    elsif(rising_edge(CLK)) then
      counter <= (counter + 1);
    end if;
  end process;

  L : process(counter)
  begin
    if(counter = 5000000) then
      phase <= not(phase);

      if (phase = '1') then
        res <= '1';
        LED_temp <= LED_temp(2 downto 0) & LED_temp(3);
      else
        res <= '0';
      end if;
    else
      res <= '0';
    end if;
  end process;
  
  G: process(phase)
  begin
    if (phase = '0') then
      L_D <= (others => '0');
    else
      L_D <= LED_temp;
    end if;
  end process;
  
end A_LED;

library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

entity test_led is
  generic (
    p_TD      : time    := 1 ns;
    p_CNT_LIM : integer := 32768 - 1
  );
  port (
    clk : in  std_logic;
    led : out std_logic_vector(3 downto 0)
  );
end test_led;

architecture rtl of test_led is
  signal div_cnt_u : unsigned(31 downto 0)        := (others => '0');

  signal phase     : std_logic                    := '1';
  signal led_reg   : std_logic_vector(3 downto 0) := (0 => '1', others => '0');
begin

  counter_control_p : process(clk)
  begin
    if (rising_edge(clk)) then
      if (div_cnt_u < p_CNT_LIM) then
        div_cnt_u <= div_cnt_u + 1 after p_TD;
      else
        div_cnt_u <= (others => '0');
      end if;
    else
      NULL;
    end if;
  end process;

  phase_control_p : process(clk)
  begin
    if (rising_edge(clk)) then
      if (div_cnt_u = p_CNT_LIM) then
        phase <= not(phase) after p_TD;
      else
        NULL;
      end if;
    else
      NULL;
    end if;
  end process; --phase_control_p

  led_reg_control_p : process(clk)
  begin
    if (rising_edge(clk)) then
      if (div_cnt_u = p_CNT_LIM) then
        if (phase = '1') then
          led_reg <= led_reg(2 downto 0) & led_reg(3) after p_TD;
        else
          NULL;
        end if;
      else
        NULL;
      end if;
    else
      NULL;
    end if;
  end process; --led_reg_control_p

  out_form_logic_p : process(phase)
  begin
    if (phase = '0') then
      led <= (others => '0');
    else
      led <= led_reg;
    end if;
  end process; --out_form_logic_p

end rtl;

library ieee;
   use ieee.std_logic_1164.all;

entity test_led_tb is
   generic (
      p_TD    : time := 1 ns;
      p_CLK_T : time := 4 ns
   );
end test_led_tb;

architecture behav of test_led_tb is
   signal clk : std_logic                    := '0';
   signal led : std_logic_vector(3 downto 0);

   component test_led is
     generic (
       p_TD      : time    := 1 ns;
       p_CNT_LIM : integer := 32768 - 1
     );
     port (
       clk : in  std_logic;
       led : out std_logic_vector(3 downto 0)
     );
   end component;
begin
   clk_gen_p : process
   begin
      clk <= not(clk);
      wait for p_CLK_T / 2;
   end process;

   UUT : test_led
      generic map (
         p_TD => p_TD
      )
      port map (
         clk => clk,
         led => led
      );
end behav;