library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity LED is
port( CLK : in std_logic;
L_D : out std_logic_vector(3 downto 0)); -- поправил у меня 4 светодиода подключены
end LED;

architecture A_LED of LED is
signal counter : std_logic_vector(20 downto 0):= (others => '0');
signal LED_temp : std_logic_vector(3 downto 0) := (0 => '1',others =>'0'); -- поправил на 4 светодиода
signal res : std_logic := '0';
begin
count : process(CLK,res)
begin
if(res = '1') then
counter <= (others => '0');
elsif(rising_edge(CLK)) then
counter <= counter +1;
end if;
end process;

L : process(counter)
begin
if(counter = 2000000) then
res <= '1';
LED_temp <= LED_temp(2 downto 0) & LED_temp(3);
-- вращаю выходной вектор по кругу налево, постоянно смещая на 1 разряд
else
res <= '0';
end if;
end process;

L_D <= led_temp; -- выдаю информацию из регистров в порт

end A_LED;

signal counter : std_logic_vector(22 downto 0):= (others => '0');
signal LED_temp : std_logic_vector(3 downto 0) := (0 => '1',others =>'0');
signal res : std_logic := '0';
signal phase : std_logic;
begin
  count : process(CLK,res)
  begin
    if(res = '1') then
      counter <= (others => '0');
    elsif(rising_edge(CLK)) then
      counter <= (counter + 1);
    end if;
  end process;
L : process(counter)
  begin
    if(counter = 5000000) then
      res <= '1';
    LED_temp <= LED_temp(2 downto 0) & LED_temp(3);
    phase <= not(phase);
   else
      res <= '0';
    end if;
  end process;
  
G: process (phase)
begin
if (phase = '0') then
L_D <= (others => '0');
else
L_D <= LED_temp;
end if;
end process;

L_D <= led_temp; --  сигнал из регистров в порт
end A_LED;

signal res      : std_logic                     := '0';
signal phase    : std_logic                     := '0';
signal LED_temp : std_logic_vector( 3 downto 0) := (0 => '1', others =>'0');
signal counter  : std_logic_vector(22 downto 0) := (others => '0');

begin
  count : process(CLK, res)
  begin
    if(res = '1') then
      counter <= (others => '0');
    elsif(rising_edge(CLK)) then
      counter <= (counter + 1);
    end if;
  end process;

  L : process(counter)
  begin
    if(counter = 5000000) then
      phase <= not(phase);

      if (phase = '1') then
        res <= '1';
        LED_temp <= LED_temp(2 downto 0) & LED_temp(3);
      else
        res <= '0';
      end if;
    else
      res <= '0';
    end if;
  end process;
  
  G: process(phase)
  begin
    if (phase = '0') then
      L_D <= (others => '0');
    else
      L_D <= LED_temp;
    end if;
  end process;
  
end A_LED;

library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

entity test_led is
  generic (
    p_TD      : time    := 1 ns;
    p_CNT_LIM : integer := 32768 - 1
  );
  port (
    clk : in  std_logic;
    led : out std_logic_vector(3 downto 0)
  );
end test_led;

architecture rtl of test_led is
  signal div_cnt_u : unsigned(31 downto 0)        := (others => '0');

  signal phase     : std_logic                    := '1';
  signal led_reg   : std_logic_vector(3 downto 0) := (0 => '1', others => '0');
begin

  counter_control_p : process(clk)
  begin
    if (rising_edge(clk)) then
      if (div_cnt_u < p_CNT_LIM) then
        div_cnt_u <= div_cnt_u + 1 after p_TD;
      else
        div_cnt_u <= (others => '0');
      end if;
    else
      NULL;
    end if;
  end process;

  phase_control_p : process(clk)
  begin
    if (rising_edge(clk)) then
      if (div_cnt_u = p_CNT_LIM) then
        phase <= not(phase) after p_TD;
      else
        NULL;
      end if;
    else
      NULL;
    end if;
  end process; --phase_control_p

  led_reg_control_p : process(clk)
  begin
    if (rising_edge(clk)) then
      if (div_cnt_u = p_CNT_LIM) then
        if (phase = '1') then
          led_reg <= led_reg(2 downto 0) & led_reg(3) after p_TD;
        else
          NULL;
        end if;
      else
        NULL;
      end if;
    else
      NULL;
    end if;
  end process; --led_reg_control_p

  out_form_logic_p : process(phase)
  begin
    if (phase = '0') then
      led <= (others => '0');
    else
      led <= led_reg;
    end if;
  end process; --out_form_logic_p

end rtl;

library ieee;
   use ieee.std_logic_1164.all;

entity test_led_tb is
   generic (
      p_TD    : time := 1 ns;
      p_CLK_T : time := 4 ns
   );
end test_led_tb;

architecture behav of test_led_tb is
   signal clk : std_logic                    := '0';
   signal led : std_logic_vector(3 downto 0);

   component test_led is
     generic (
       p_TD      : time    := 1 ns;
       p_CNT_LIM : integer := 32768 - 1
     );
     port (
       clk : in  std_logic;
       led : out std_logic_vector(3 downto 0)
     );
   end component;
begin
   clk_gen_p : process
   begin
      clk <= not(clk);
      wait for p_CLK_T / 2;
   end process;

   UUT : test_led
      generic map (
         p_TD => p_TD
      )
      port map (
         clk => clk,
         led => led
      );
end behav;

    else
      NULL;
    end if;

    a ^= b ^= a ^= b;

library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

entity test_led is
  generic (
    p_TD      : time    := 1 ns;
    p_CNT_LIM : integer := 5000000-1                      
  );
  port (
    clk : in  std_logic;
    btn : in  std_logic; кнопка
    led : out std_logic_vector(7 downto 0)
  );
end test_led;

architecture rtl of test_led is
  signal div_cnt_u : unsigned(22 downto 0)        := (others => '0');
  signal phase     : std_logic                    := '1';
  signal btn_tu    : std_logic                    : ='1'; -сигнал при нажатии кнопки
  signal led_reg   : std_logic_vector(7 downto 0) := (0 => '1', others => '0');
begin

btn_control: process(clk)
begin
  if rising_edge(clk) then
    btn_tu <= btn;
    if btn_tu = '0' and btn = '1' then
      led_reg <= led_reg + 1;
    end if;
  end if;
end process;

counter_control_p: process(clk)
  begin
    if (rising_edge(clk)) then
      if (div_cnt_u < p_CNT_LIM) then
        div_cnt_u <= div_cnt_u + 1 after p_TD;
      else
        div_cnt_u <= (others => '0');
      end if;
    else
      NULL;
    end if;
  end process;

phase_control_p: process(clk)
  begin
    if (rising_edge(clk)) then
      if (div_cnt_u = p_CNT_LIM) then
        phase <= not(phase) after p_TD;
      else
        NULL;
      end if;
    else
      NULL;
    end if;
  end process; --phase_control_p

led_reg_control_p: process(clk)
  begin
    if (rising_edge(clk)) then
      if (div_cnt_u = p_CNT_LIM) then
        if (phase = '1') then
          led_reg <= led_reg(6 downto 0) & led_reg(7) after p_TD;
          NULL;
        end if;
      else
        NULL;
      end if;
    else
      NULL;
    end if;
  end process; --led_reg_control_p

out_form_logic_p: process(phase)
  begin
    if (phase = '0') then
      led <= (others => '0');
    else
      led <= led_reg;
    end if;
  end process; --out_form_logic_p

end rtl;

library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

entity test_led is
  generic (
    p_TD      : time    := 1 ns;
    p_CNT_LIM : integer := 5000000-1                      
  );
  port (
    clk : in  std_logic;
    --btn : in  std_logic; --кнопка
    led : out std_logic_vector(7 downto 0)
  );
end test_led;

architecture rtl of test_led is
  signal div_cnt_u : unsigned(22 downto 0)        := (others => '0');
  signal phase     : std_logic                    := '1';
  signal btn_ce    : std_logic                    := '0'; --сигнал при нажатии кнопки
  signal led_reg   : std_logic_vector(7 downto 0) := (0 => '1', others => '0');
begin

counter_control_p: process(clk)
  begin
    if (rising_edge(clk)) then
      if (div_cnt_u < p_CNT_LIM) then
        div_cnt_u <= div_cnt_u + 1 after p_TD;
      else
        div_cnt_u <= (others => '0');
      end if;
    else
      NULL;
    end if;
  end process;

phase_control_p: process(clk)
  begin
    if (rising_edge(clk)) then
      if (div_cnt_u = p_CNT_LIM) then
        phase <= not(phase) after p_TD;
      else
        NULL;
      end if;
    else
      NULL;
    end if;
  end process; --phase_control_p

led_reg_control_p: process(clk)
  begin
    if (rising_edge(clk)) then
      if (div_cnt_u = p_CNT_LIM) then
        if (phase = '1') then
          led_reg <= led_reg(6 downto 0) & led_reg(7) after p_TD;
          NULL;
        end if;
      else
        NULL;
      end if;
    else
      NULL;
    end if;
  end process; --led_reg_control_p
  
btn_control: process(clk) -- нажатия кнопки
  begin
   if (btn_ce = '1') then
       btn_ce <= not(btn_ce)
       phase <= (others => '0');
       else
       phase <= '1';
   end if;
  end process;
  
out_form_logic_p: process(phase)
  begin
    if (phase = '0') then
      led <= (others => '0');
    else
      led <= led_reg;
    end if;
  end process; --out_form_logic_p

end rtl;

library ieee;
   use ieee.std_logic_1164.all;

entity test_led_tb is
   generic (
      p_TD    : time := 1 ns;
      p_CLK_T : time := 4 ns
   );
end test_led_tb;

architecture behav of test_led_tb is
   signal clk : std_logic                    := '0';
   signal sw  : std_logic                    := '0';
   signal led : std_logic_vector(3 downto 0);

   component test_led is
     generic (
       p_TD      : time    := 1 ns;
       p_CNT_LIM : integer := 1000 - 1
     );
     port (
       clk : in  std_logic;
       sw  : in  std_logic;
       led : out std_logic_vector(3 downto 0)
     );
   end component;
begin
  clk_gen_p : process
  begin
    clk <= not(clk);
    wait for p_CLK_T / 2;
  end process;

  sw <= '1' after 100 us, '0' after 101 us, '1' after 200 us;

  UUT : test_led
    generic map (
      p_TD => p_TD
    )
    port map (
      clk => clk,
      sw  => sw,
      led => led
    );

end behav;

library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

entity test_led is
  generic (
    p_TD      : time    := 1 ns;
    p_CNT_LIM : integer := 32768 - 1
  );
  port (
    clk : in  std_logic;
    sw  : in  std_logic;
    led : out std_logic_vector(3 downto 0)
  );
end test_led;

architecture rtl of test_led is
  type on_off_state is (OFF, ONN);
  signal led_state  : on_off_state                 := OFF;

  signal div_cnt_u  : unsigned(31 downto 0)        := (others => '0');

  signal phase      : std_logic                    := '1';
  signal sw_sync_re : std_logic                    := '0';
  signal sw_reg     : std_logic_vector(2 downto 0);
  signal led_reg    : std_logic_vector(3 downto 0) := (0 => '1', others => '0');
begin

  resync_sw_p : process(clk)
  begin
    if (rising_edge(clk)) then
      sw_reg(0)          <= sw                 after p_TD;
      sw_reg(2 downto 1) <= sw_reg(1 downto 0) after p_TD;
    else
      NULL;
    end if;
  end process; --resync_sw_p

  sw_sync_re <= sw_reg(1) and not(sw_reg(2));

  scheme_state_control_p : process(clk)
  begin
    if (rising_edge(clk)) then
      if (sw_sync_re = '1') then
        if (led_state = ONN) then
          led_state <= OFF after p_TD;
        else
          led_state <= ONN after p_TD;
        end if;
      else
        NULL;
      end if;
    else
      NULL;
    end if;
  end process; --scheme_state_control_p

  counter_control_p : process(clk)
  begin
    if (rising_edge(clk)) then
      if (div_cnt_u < p_CNT_LIM) then
        div_cnt_u <= div_cnt_u + 1 after p_TD;
      else
        div_cnt_u <= (others => '0');
      end if;
    else
      NULL;
    end if;
  end process;

  phase_control_p : process(clk)
  begin
    if (rising_edge(clk)) then
      if (div_cnt_u = p_CNT_LIM) then
        if (phase = '0') then
          if (led_state = ONN) then
            phase <= '1' after p_TD;
          else
            phase <= '0' after p_TD;
          end if;
        else
          phase <= '0' after p_TD;
        end if;
      else
        NULL;
      end if;
    else
      NULL;
    end if;
  end process; --phase_control_p

  led_reg_control_p : process(clk)
  begin
    if (rising_edge(clk)) then
      if (div_cnt_u = p_CNT_LIM) then
        if (phase = '1') then
          led_reg <= led_reg(2 downto 0) & led_reg(3) after p_TD;
        else
          NULL;
        end if;
      else
        NULL;
      end if;
    else
      NULL;
    end if;
  end process; --led_reg_control_p

  out_form_logic_p : process(phase)
  begin
    if (phase = '0') then
      led <= (others => '0');
    else
      led <= led_reg;
    end if;
  end process; --out_form_logic_p

end rtl;

sw <= '0' after 0 ms, '1' after 3000  ms, '0' after 6000 ms, '1'after 10000 ms;

`timescale 1ns / 1ps

//----- top module

module led_blink(
input clock,
input sw,
output reg [3:0] led
);

initial led = 0;
reg [3:0] state;
initial state = 4'b1000;

reg on1off0;
initial on1off0 = 1;

reg [23:0] divider;
initial divider = 0;
always @(posedge clock) begin
    if(divider < 499999) divider <= divider + 1;
    else begin
        divider <= 0;
        if(sw) begin
            on1off0 <= !on1off0;
            if(on1off0) begin
                state <= {state[0], state[3:1]};
                led <= state;
            end else led <= 0;
        end else begin
            on1off0 <= 1;
            led <= 0;
        end
    end
end

endmodule

//----- testbench

module testbench();

    reg clock1m; // 1 MHz
    initial clock1m = 0;
    always clock1m = #500 !clock1m;

    reg sw;
    wire [3:0] leds;

    led_blink uut(
    .clock(clock1m),
    .led(leds),
    .sw(sw));
    
    initial begin
        sw = 0;
        
        #999999000;
        #1000000000;
        #1000000000;
        
        sw = 1;
        
        #1000000000;
        #1000000000;
        #1000000000;
        
        sw = 0;
        
        #1000000000;
        #1000000000;
        #1000000000;
        #1000000000;
        
        sw = 1;
        
        #1000000000;
        #1000000000;
        #1000000000;
        #1000000000;
        #1000000000;
        
        sw = 0;
        
        #1000000000;
        #1000000000;
        #1000000000;
        
        $stop;
    end

endmodule

library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

entity led_blink is
  port (
    clk : in  std_logic;
    sw  : in  std_logic;
    led : out std_logic_vector(3 downto 0)
  );
end led_blink;

architecture rtl of led_blink is
  signal on1off0 : std_logic                    := '1';
  signal state   : std_logic_vector(3 downto 0) := "0001";
  signal divider : unsigned(23 downto 0)        := (others => '0');
begin
  main_p : process(clk)
  begin
    if (rising_edge(clk)) then
      if (divider < 200) then
        divider <= divider + 1;
      else
        divider <= (others => '0');
        if (sw = '1') then
          on1off0 <= not(on1off0);
          if (on1off0 = '1') then
            state <= state(2 downto 0) & state(3);
            led   <= state;
          else
            led   <= (others => '0');
          end if;
        else
          on1off0 <= '1';
          led     <= (others => '0');
        end if;
      end if;
    end if;
  end process;
end rtl;