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 помогите найти общий язык, Quartus 16.1.2 |
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 Sep 8 2017, 14:10
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я только учусь...
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Пожалуйста помогите разобраться. Квартус выдает ошибку Цитата Error (10327): VHDL error at SMC.vhd(68): can't determine definition of operator ""sra"" -- found 0 possible definitions
Error (10411): VHDL Type Conversion error at SMC.vhd(68): can't determine type of object or expression near text or symbol "std_logic_vector" в проекте стоит галочка использовать VHDL 2008 ошибка возникает в следующем описании: Код library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity SMC is
generic ( M : natural := 32 );
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
Tmax : in STD_LOGIC_VECTOR (31 downto 0); -- maximum timing
Nsegment : in STD_LOGIC_VECTOR (7 downto 0); -- total segment acceleration/deceleration
T0 : in STD_LOGIC_VECTOR (31 downto 0);
--Duty_cycle : in STD_LOGIC_VECTOR (15 downto 0);
--ready_period : out STD_LOGIC;
out_shim : out STD_LOGIC );
end SMC;
architecture Behavioral of SMC is
COMPONENT shim
generic ( N : natural := 3 );
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
--load : in STD_LOGIC;
Period : in STD_LOGIC_VECTOR (N-1 downto 0);
Duty_cycle : in STD_LOGIC_VECTOR (N-1 downto 0);
ready_period : out STD_LOGIC;
out_shim : out STD_LOGIC );
END COMPONENT;
signal reg_period : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_duty_cycle : STD_LOGIC_VECTOR (M-1 downto 0);
signal count_period : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_number_of_steps : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_ready_period, reg_segment_ready : STD_LOGIC;
signal reg_en_shim, reg_load_shim : STD_LOGIC;
signal cnt_segments : STD_LOGIC_VECTOR (15 downto 0);
signal reg_number_of_segments : STD_LOGIC_VECTOR (M-1 downto 0);
signal cnt : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_duty_segment : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_ena_work : STD_LOGIC;
begin
shim_inst : shim
generic map (
N => M)
port map
(
clk => clk,
rst => rst,
en => reg_en_shim,
--load => reg_load_shim,
Period => reg_period,
Duty_cycle => reg_duty_cycle,
ready_period => reg_ready_period,
out_shim => out_shim
);
reg_en_shim <= '1';
reg_duty_cycle <= std_logic_vector (unsigned(reg_period) sra 1);
process (all)
begin
if rst = '1' then
count_period <= (others=>'0');
reg_period <= T0;
reg_number_of_segments <= std_logic_vector (unsigned(Tmax) sra conv_integer(Nsegment));
reg_duty_segment <= std_logic_vector (unsigned(Tmax) sra 0);
reg_segment_ready <= '0';
elsif(rising_edge(clk)) then
if reg_ena_work = '1' then
if cnt = reg_duty_segment then -- k
reg_period <= std_logic_vector (unsigned(reg_period) sra 1);
reg_segment_ready <= '1';
reg_duty_segment <= std_logic_vector (unsigned(Tmax) sra conv_integer(cnt_segments+1));
else
reg_segment_ready <= '0';
if reg_ready_period = '1' then
count_period <= count_period + "0000000000000001";
end if;
end if;
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
cnt_segments <= (others=>'0');
cnt <= (others=>'0');
elsif(rising_edge(clk)) then
if reg_segment_ready = '1' then
cnt_segments <= cnt_segments + "0000000000000001";
cnt <= (others=>'0');
else
cnt <= cnt + 1;
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
reg_ena_work <= '0';
elsif(rising_edge(clk)) then
if (cnt_segments = Nsegment) then
reg_ena_work <= '0';
elsif en = '1' then
reg_ena_work <= '1';
end if;
end if;
end process;
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
entity shim is
generic ( N : natural := 3 );
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
--load : in STD_LOGIC;
Period : in STD_LOGIC_VECTOR (N-1 downto 0);
Duty_cycle : in STD_LOGIC_VECTOR (N-1 downto 0);
ready_period : out STD_LOGIC;
out_shim : out STD_LOGIC );
end shim;
architecture Behavioral of shim is
signal count_shim : STD_LOGIC_VECTOR (N-1 downto 0);
signal reg_Period : STD_LOGIC_VECTOR (N-1 downto 0);
signal reg_Duty_cycle : STD_LOGIC_VECTOR (N-1 downto 0);
begin
process (all)
begin
if rst = '1' then
count_shim <= (others=>'0');
elsif(rising_edge(clk)) then
if en = '1' then
if count_shim = reg_Period then
ready_period <= '1';
count_shim <= (others=>'0');
else
count_shim <= count_shim + std_logic_vector( to_unsigned(1, count_shim'length ));
ready_period <= '0';
end if;
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
out_shim <= '0';
elsif(rising_edge(clk)) then
if count_shim < reg_Duty_cycle then
out_shim <= '1';
else
out_shim <= '0';
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
reg_Period <= (others=>'0');
reg_Duty_cycle <= (others=>'0');
elsif(rising_edge(clk)) then
if ready_period = '1' then
reg_Period <= Period;
reg_Duty_cycle <= Duty_cycle;
end if;
end if;
end process;
end Behavioral; ошибка ссылается на строку reg_duty_cycle <= std_logic_vector (unsigned(reg_period) sra 1); Моделсим 10.5 ошибок не выдает - моделирует...
--------------------
If it doesn't work in simulation, it won't work on the board.
"Ты живешь в своих поступках, а не в теле. Ты — это твои действия, и нет другого тебя" Антуан де Сент-Экзюпери повесть "Маленький принц"
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Sep 8 2017, 15:31
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Гуру
Группа: Свой
Сообщений: 2 220
Регистрация: 21-10-04
Из: Balakhna
Пользователь №: 937
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--use IEEE.STD_LOGIC_UNSIGNED.ALL; - это никогда не использовать. use ieee.numeric_std.all; - только это и соответственно srl. ------------------------------------------------------------------------------ -- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE StdL 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.11 function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: SHIFT_RIGHT(ARG, COUNT) -- Id: S.2 function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a shift-right on an UNSIGNED vector COUNT times. -- The vacated positions are filled with '0'. -- The COUNT rightmost elements are lost. https://standards.ieee.org/downloads/1076/1...umeric_std.vhdl
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Sep 11 2017, 09:21
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Гуру
Группа: Свой
Сообщений: 2 220
Регистрация: 21-10-04
Из: Balakhna
Пользователь №: 937
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Цитата(_Anatoliy @ Sep 11 2017, 11:58)  Да это не вывод, это вопрос, для себя вывод я сделал давно. Просто хочется знать что думают коллеги. ссылкаВедь мои самописные библиотеки никто не стандартизировал. Дело не в стандартизированности, обе библиотеки стандартизированы, обе библиотеки определяют знаковые типы и операции с ними, какую из них компилятор должен использовать? Это просто ошибка и бестолковщина, как минимум использовать нужно какую-то одну, лучше последнюю стандартизированную numeric_std, но ни в коем случае не обе одновременно в одном entity.
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Sep 12 2017, 08:17
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я только учусь...
Группа: Модераторы
Сообщений: 3 447
Регистрация: 29-01-07
Из: Украина
Пользователь №: 24 839
|
исправил так Код library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity SMC is
generic ( M : natural := 32 );
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
Tmax : in STD_LOGIC_VECTOR (31 downto 0); -- maximum timing
Nsegment : in STD_LOGIC_VECTOR (7 downto 0); -- total segment acceleration/deceleration
T0 : in STD_LOGIC_VECTOR (31 downto 0);
--Duty_cycle : in STD_LOGIC_VECTOR (15 downto 0);
--ready_period : out STD_LOGIC;
out_shim : out STD_LOGIC );
end SMC;
architecture Behavioral of SMC is
COMPONENT shim
generic ( N : natural := 3 );
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
--load : in STD_LOGIC;
Period : in STD_LOGIC_VECTOR (N-1 downto 0);
Duty_cycle : in STD_LOGIC_VECTOR (N-1 downto 0);
ready_period : out STD_LOGIC;
out_shim : out STD_LOGIC );
END COMPONENT;
signal reg_period : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_duty_cycle : STD_LOGIC_VECTOR (M-1 downto 0);
signal count_period : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_number_of_steps : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_ready_period, reg_segment_ready : STD_LOGIC;
signal reg_en_shim, reg_load_shim : STD_LOGIC;
signal cnt_segments, cnt_segments1 : STD_LOGIC_VECTOR (15 downto 0);
signal reg_number_of_segments : STD_LOGIC_VECTOR (M-1 downto 0);
signal cnt : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_duty_segment : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_ena_work : STD_LOGIC;
begin
shim_inst : shim
generic map (
N => M)
port map
(
clk => clk,
rst => rst,
en => reg_en_shim,
--load => reg_load_shim,
Period => reg_period,
Duty_cycle => reg_duty_cycle,
ready_period => reg_ready_period,
out_shim => out_shim
);
reg_en_shim <= '1';
reg_duty_cycle <= std_logic_vector (SHIFT_RIGHT(unsigned(reg_period), 1));
cnt_segments1 <= std_logic_vector (unsigned(cnt_segments) + 1);
process (all)
begin
if rst = '1' then
count_period <= (others=>'0');
reg_period <= T0;
reg_number_of_segments <= std_logic_vector (SHIFT_RIGHT(unsigned(Tmax), to_integer(unsigned(Nsegment))));
reg_duty_segment <= std_logic_vector (SHIFT_RIGHT(unsigned(Tmax), 0));
reg_segment_ready <= '0';
elsif(rising_edge(clk)) then
if reg_ena_work = '1' then
if cnt = reg_duty_segment then -- k
reg_period <= std_logic_vector (SHIFT_RIGHT(unsigned(reg_period), 1));
reg_segment_ready <= '1';
reg_duty_segment <= std_logic_vector (SHIFT_RIGHT(unsigned(Tmax), to_integer(unsigned(cnt_segments1))));
else
reg_segment_ready <= '0';
if reg_ready_period = '1' then
count_period <= count_period + "0000000000000001";
end if;
end if;
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
cnt_segments <= (others=>'0');
cnt <= (others=>'0');
elsif(rising_edge(clk)) then
if reg_segment_ready = '1' then
cnt_segments <= cnt_segments + "0000000000000001";
cnt <= (others=>'0');
else
cnt <= cnt + 1;
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
reg_ena_work <= '0';
elsif(rising_edge(clk)) then
if (cnt_segments = Nsegment) then
reg_ena_work <= '0';
elsif en = '1' then
reg_ena_work <= '1';
end if;
end if;
end process;
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
entity shim is
generic ( N : natural := 3 );
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
--load : in STD_LOGIC;
Period : in STD_LOGIC_VECTOR (N-1 downto 0);
Duty_cycle : in STD_LOGIC_VECTOR (N-1 downto 0);
ready_period : out STD_LOGIC;
out_shim : out STD_LOGIC );
end shim;
architecture Behavioral of shim is
signal count_shim : STD_LOGIC_VECTOR (N-1 downto 0);
signal reg_Period : STD_LOGIC_VECTOR (N-1 downto 0);
signal reg_Duty_cycle : STD_LOGIC_VECTOR (N-1 downto 0);
begin
process (all)
begin
if rst = '1' then
count_shim <= (others=>'0');
elsif(rising_edge(clk)) then
if en = '1' then
if count_shim = reg_Period then
ready_period <= '1';
count_shim <= (others=>'0');
else
count_shim <= count_shim + std_logic_vector( to_unsigned(1, count_shim'length ));
ready_period <= '0';
end if;
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
out_shim <= '0';
elsif(rising_edge(clk)) then
if count_shim < reg_Duty_cycle then
out_shim <= '1';
else
out_shim <= '0';
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
reg_Period <= (others=>'0');
reg_Duty_cycle <= (others=>'0');
elsif(rising_edge(clk)) then
if ready_period = '1' then
reg_Period <= Period;
reg_Duty_cycle <= Duty_cycle;
end if;
end if;
end process;
end Behavioral; ошибка Цитата Error (10327): VHDL error at SMC.vhd(90): can't determine definition of operator ""+"" -- found 0 possible definitions во втором описании тоже тогда надо убирать библиотеку - use ieee.std_logic_unsigned.all;
--------------------
If it doesn't work in simulation, it won't work on the board.
"Ты живешь в своих поступках, а не в теле. Ты — это твои действия, и нет другого тебя" Антуан де Сент-Экзюпери повесть "Маленький принц"
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Sep 12 2017, 08:34
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В поисках себя...
Группа: Свой
Сообщений: 729
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Из: Санкт-Петербург
Пользователь №: 77 140
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Цитата(Maverick @ Sep 12 2017, 11:17) Ну так и правильно, операция + не определена для SLV. Хотите счетчик на SLV, тогда явно преобразуйте типы, например: Код count_period <= std_logic_vector(unsigned(count_period) + 1);
cnt_segments <= std_logic_vector(unsigned(cnt_segments) + 1);
cnt <= std_logic_vector(unsigned(cnt) + 1); Или сразу объявляйте счетчики как UNSIGNED, тогда можно обойтись такой записью: Код count_period <= count_period + "1";
cnt_segments <= cnt_segments + "1";
cnt <= cnt + "1"; ;
Сообщение отредактировал Flip-fl0p - Sep 12 2017, 08:39
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Sep 12 2017, 08:42
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я только учусь...
Группа: Модераторы
Сообщений: 3 447
Регистрация: 29-01-07
Из: Украина
Пользователь №: 24 839
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в чем разница Цитата cnt_segments1 <= std_logic_vector (unsigned(cnt_segments) + 1); у меня сделано так ??? PS это ошибка для первого описания....
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If it doesn't work in simulation, it won't work on the board.
"Ты живешь в своих поступках, а не в теле. Ты — это твои действия, и нет другого тебя" Антуан де Сент-Экзюпери повесть "Маленький принц"
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Sep 12 2017, 08:49
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В поисках себя...
Группа: Свой
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Регистрация: 11-06-13
Из: Санкт-Петербург
Пользователь №: 77 140
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Цитата(Maverick @ Sep 12 2017, 11:42) в чем разница
у меня сделано так
???
PS это ошибка для первого описания.... Так во втором описании так-же присутствует эта ошибка: Код count_period <= count_period + "0000000000000001";
Сообщение отредактировал Flip-fl0p - Sep 12 2017, 08:50
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Sep 12 2017, 09:22
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я только учусь...
Группа: Модераторы
Сообщений: 3 447
Регистрация: 29-01-07
Из: Украина
Пользователь №: 24 839
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Цитата(Flip-fl0p @ Sep 12 2017, 11:49) спасибо...  тему можно закрывать... да, получилось следующим образом: Код library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity SMC is
generic ( M : natural := 32 );
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
load : in STD_LOGIC;
Tmax : in STD_LOGIC_VECTOR (31 downto 0); -- maximum timing
Nsegment : in STD_LOGIC_VECTOR (7 downto 0); -- total segment acceleration/deceleration
T0 : in STD_LOGIC_VECTOR (31 downto 0);
--Duty_cycle : in STD_LOGIC_VECTOR (15 downto 0);
--ready_period : out STD_LOGIC;
out_shim : out STD_LOGIC );
end SMC;
architecture Behavioral of SMC is
COMPONENT shim
generic ( N : natural := 3 );
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
--load : in STD_LOGIC;
Period : in STD_LOGIC_VECTOR (N-1 downto 0);
Duty_cycle : in STD_LOGIC_VECTOR (N-1 downto 0);
ready_period : out STD_LOGIC;
out_shim : out STD_LOGIC );
END COMPONENT;
signal reg_period : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_duty_cycle : STD_LOGIC_VECTOR (M-1 downto 0);
signal count_period : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_number_of_steps : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_ready_period, reg_segment_ready : STD_LOGIC;
signal reg_en_shim, reg_load_shim : STD_LOGIC;
signal cnt_segments : STD_LOGIC_VECTOR (15 downto 0);
signal reg_number_of_segments : STD_LOGIC_VECTOR (M-1 downto 0);
signal cnt : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_duty_segment : STD_LOGIC_VECTOR (M-1 downto 0);
signal reg_ena_work : STD_LOGIC;
begin
shim_inst : shim
generic map (
N => M)
port map
(
clk => clk,
rst => rst,
en => reg_en_shim,
--load => reg_load_shim,
Period => reg_period,
Duty_cycle => reg_duty_cycle,
ready_period => reg_ready_period,
out_shim => out_shim
);
reg_en_shim <= '1';
reg_duty_cycle <= std_logic_vector (SHIFT_RIGHT(unsigned(reg_period), 1));
process (all)
begin
if rst = '1' then
count_period <= (others=>'0');
reg_period <= (others=>'0');
reg_number_of_segments <= (others=>'0');
reg_duty_segment <= (others=>'0');
reg_segment_ready <= '0';
elsif(rising_edge(clk)) then
if load = '1' and reg_ena_work = '0' then
reg_period <= T0;
reg_number_of_segments <= std_logic_vector (SHIFT_RIGHT(unsigned(Tmax), to_integer(unsigned(Nsegment))));
reg_duty_segment <= std_logic_vector (SHIFT_RIGHT(unsigned(Tmax), 0));
end if;
if reg_ena_work = '1' and load = '0' then
if cnt = reg_duty_segment then -- k
reg_period <= std_logic_vector (SHIFT_RIGHT(unsigned(reg_period), 1));
reg_segment_ready <= '1';
reg_duty_segment <= std_logic_vector (SHIFT_RIGHT(unsigned(Tmax), to_integer(unsigned(cnt_segments) +1 )));
else
reg_segment_ready <= '0';
if reg_ready_period = '1' then
count_period <= std_logic_vector (unsigned(count_period) + 1);
end if;
end if;
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
cnt_segments <= (others=>'0');
cnt <= (others=>'0');
elsif(rising_edge(clk)) then
if reg_segment_ready = '1' then
cnt_segments <= std_logic_vector (unsigned(cnt_segments) + 1);
cnt <= (others=>'0');
else
cnt <= std_logic_vector (unsigned(cnt) + 1);
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
reg_ena_work <= '0';
elsif(rising_edge(clk)) then
if (unsigned(cnt_segments) = unsigned(Nsegment)) then
reg_ena_work <= '0';
elsif en = '1' then
reg_ena_work <= '1';
end if;
end if;
end process;
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
entity shim is
generic ( N : natural := 3 );
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
en : in STD_LOGIC;
--load : in STD_LOGIC;
Period : in STD_LOGIC_VECTOR (N-1 downto 0);
Duty_cycle : in STD_LOGIC_VECTOR (N-1 downto 0);
ready_period : out STD_LOGIC;
out_shim : out STD_LOGIC );
end shim;
architecture Behavioral of shim is
signal count_shim : STD_LOGIC_VECTOR (N-1 downto 0);
signal reg_Period : STD_LOGIC_VECTOR (N-1 downto 0);
signal reg_Duty_cycle : STD_LOGIC_VECTOR (N-1 downto 0);
begin
process (all)
begin
if rst = '1' then
count_shim <= (others=>'0');
elsif(rising_edge(clk)) then
if en = '1' then
if count_shim = reg_Period then
ready_period <= '1';
count_shim <= (others=>'0');
else
count_shim <= std_logic_vector (unsigned(count_shim) + 1);
ready_period <= '0';
end if;
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
out_shim <= '0';
elsif(rising_edge(clk)) then
if count_shim < reg_Duty_cycle then
out_shim <= '1';
else
out_shim <= '0';
end if;
end if;
end process;
process (all)
begin
if rst = '1' then
reg_Period <= (others=>'0');
reg_Duty_cycle <= (others=>'0');
elsif(rising_edge(clk)) then
if ready_period = '1' then
reg_Period <= Period;
reg_Duty_cycle <= Duty_cycle;
end if;
end if;
end process;
end Behavioral;
--------------------
If it doesn't work in simulation, it won't work on the board.
"Ты живешь в своих поступках, а не в теле. Ты — это твои действия, и нет другого тебя" Антуан де Сент-Экзюпери повесть "Маленький принц"
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