Library ieee;
Use ieee.std_logic_1164.all;

Entity shift is
  Port(C, SI : in  std_logic;
        SO : out std_logic);
End shift;

Architecture archi of shift is
  Signal tmp: std_logic_vector(6 downto 0);
  Begin
    Process (C)
      Begin
        If (c'event and C='1') then
          For i in 0 to 5 loop
            Tmp(i+1) <= tmp(i);
          End loop;
          Tmp(0) <= SI;
        End if;
    End process;
    SO <= tmp(6);
End archi;

library ieee;
    use ieee.std_logic_1164.all;

entity shift_reg is
    port
    (
        clk      : in  std_logic;                            
        data_in  : in  std_logic;                        
        data_out : out std_logic                            
    );
end entity;

architecture RTL of shift_reg is
    signal reg : std_logic_vector(7 downto 0) := (others => '0');    
begin

    shift_reg_proc : process(clk)
    begin
        if (rising_edge(clk)) then                 -- по каждому переднему фронту
            reg <= data_in & reg(7 downto 1);      -- Сдвинем данные вправо на 1 разряд.
        end if;
    end process;
    
    data_out <= reg(0);                      

end architecture;