Код
Library ieee;
Use ieee.std_logic_1164.all;
Entity shift is
Port(C, SI : in std_logic;
SO : out std_logic);
End shift;
Architecture archi of shift is
Signal tmp: std_logic_vector(6 downto 0);
Begin
Process (C)
Begin
If (c'event and C='1') then
For i in 0 to 5 loop
Tmp(i+1) <= tmp(i);
End loop;
Tmp(0) <= SI;
End if;
End process;
SO <= tmp(6);
End archi;
Use ieee.std_logic_1164.all;
Entity shift is
Port(C, SI : in std_logic;
SO : out std_logic);
End shift;
Architecture archi of shift is
Signal tmp: std_logic_vector(6 downto 0);
Begin
Process (C)
Begin
If (c'event and C='1') then
For i in 0 to 5 loop
Tmp(i+1) <= tmp(i);
End loop;
Tmp(0) <= SI;
End if;
End process;
SO <= tmp(6);
End archi;