module ram_blocks(
    input clk,
    input [15:0]addr,
    input [15:0]data,
    input wr,
    
    output [15:0]data_1,
    output [15:0]data_2,
    output [15:0]data_3,
    output [15:0]data_4,
    output [15:0]data_5,
    output [15:0]data_6,
    output [15:0]data_7,
    output [15:0]data_8,
    output [15:0]data_9,
    output [15:0]data_10,
    output [15:0]data_11,
    output [15:0]data_12,
    output [15:0]data_13,
    output [15:0]data_14,
    output [15:0]data_15,
    output [15:0]data_16);
    
    wire     [15:0]data_out[15:0];
    wire     [16:0]s;
    
    genvar i;
    generate
    for(i = 0; i < 16; i = i + 1)
    begin : ram_generation
        assign s[i] = addr[i] & wr;
        ram     ram_inst(.data(data), .wren(s[i]), .address(1'b1), .clock(clk), .q(data_out[i]));        
    end
    endgenerate

    assign data_1 = data_out[0];
    assign data_2 = data_out[1];
    assign data_3 = data_out[2];
    assign data_4 = data_out[3];
    assign data_5 = data_out[4];
    assign data_6 = data_out[5];
    assign data_7 = data_out[6];
    assign data_8 = data_out[7];
    assign data_9 = data_out[8];
    assign data_10 = data_out[9];
    assign data_11 = data_out[10];
    assign data_12 = data_out[11];
    assign data_13 = data_out[12];
    assign data_14 = data_out[13];
    assign data_15 = data_out[14];
    assign data_16 = data_out[15];
        
endmodule

    wire     w_cs
    reg     dff_out;
    
    always @(posedge clk)
    begin
        dff_out <= cs;
    end
    assign w_cs = dff_out;

# ** Warning: (vsim-3009) [TSCALE] - Module 'ram_blocks' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb/main_inst_tb/mem_block1/ram_blocks1
# Loading work.decoder
# ** Warning: (vsim-3009) [TSCALE] - Module 'decoder' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb/main_inst_tb/mem_block1/decoder1