А можно как-нибудь автоматизировать посылку разных значений по SPI? В идеале хочется иметь тестбенч такого формата, чтобы в нем задавались только 2 параметра: значение данных и время в которые они посылаются, а сама колбаса из 32-х битов проходила автоматом. Как решить эту задачку? Ставить внешний цикл for над всем тестбенчем?

module my_pll
    (
        input  wire in_clk,
        output wire out_clk0,
        output wire out_clk1
    );

    pll
        pll_inst
        (
            .inclk0     (in_clk  ),

            .c0         (out_clk0),
            .c1         (out_clk1)
        );

endmodule // my_pll

module main_inst(input clk, output clk_out, output clk_108MHz);
    pll     pll1(.c0(clk_108MHz), .inclk0(clk));
    divider divider1(.out(clk_out), .clk(clk_108MHz));
    defparam  divider1.bitnum = 25;  //Задаем параметр модуля divider
endmodule

#         Region: /tb/main_inst_tb/mem_block1/ram_blocks1
#         Searched libraries:
#             C:/altera/91sp1/Projects/cyclone III/simulation/work
# ** Error: (vsim-3033) C:/altera/91sp1/Projects/cyclone III/helper/ram/ram.v(62): Instantiation of 'altsyncram' failed. The design unit was not found.
#
#         Region: /tb/main_inst_tb/mem_block1/ram_blocks1/ram_08
#         Searched libraries:
#             C:/altera/91sp1/Projects/cyclone III/simulation/work
# ** Error: (vsim-3033) C:/altera/91sp1/Projects/cyclone III/helper/ram_blocks/ram_blocks.v(56): Instantiation of 'AND2' failed. The design unit was not found.
#         Region: /tb/main_inst_tb/mem_block1/ram_blocks1
#         Searched libraries:
#             C:/altera/91sp1/Projects/cyclone III/simulation/work
# ** Error: (vsim-3033) C:/altera/91sp1/Projects/cyclone III/helper/ram/ram.v(62): Instantiation of 'altsyncram' failed. The design unit was not found.
#
#         Region: /tb/main_inst_tb/mem_block1/ram_blocks1/ram_08
#         Searched libraries:
#             C:/altera/91sp1/Projects/cyclone III/simulation/work
# ** Error: (vsim-3033) C:/altera/91sp1/Projects/cyclone III/helper/ram_blocks/ram_blocks.v(56): Instantiation of 'AND2' failed. The design unit was not found.

AND2     AND2_01(.IN1(addr[0]), .IN2(wr), .OUT(s1));

module ram_blocks(
input clk,
input [15:0]addr,
input [15:0]data,
input wr,

output [15:0]data_1,
output [15:0]data_2,
output [15:0]data_3,
output [15:0]data_4,
output [15:0]data_5,
output [15:0]data_6,
output [15:0]data_7,
output [15:0]data_8,
output [15:0]data_9,
output [15:0]data_10,
output [15:0]data_11,
output [15:0]data_12,
output [15:0]data_13,
output [15:0]data_14,
output [15:0]data_15,
output [15:0]data_16);

wire s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16;
wire w_VCC;
assign w_VCC = 1'b1;

AND2 AND2_01(.IN1(addr[0]), .IN2(wr), .OUT(s1));
ram ram_01(.data(data), .wren(s1), .address(w_VCC), .clock(clk), .q(data_1));

AND2 AND2_02(.IN1(addr[1]), .IN2(wr), .OUT(s2));
ram ram_02(.data(data), .wren(s2), .address(1'b1), .clock(clk), .q(data_2));

AND2 AND2_03(.IN1(addr[2]), .IN2(wr), .OUT(s3));
ram ram_03(.data(data), .wren(s3), .address(1'b1), .clock(clk), .q(data_3));

AND2 AND2_04(.IN1(addr[3]), .IN2(wr), .OUT(s4));
ram ram_04(.data(data), .wren(s4), .address(1'b1), .clock(clk), .q(data_4));



AND2 AND2_05(.IN1(addr[4]), .IN2(wr), .OUT(s5));
ram ram_05(.data(data), .wren(s5), .address(1'b1), .clock(clk), .q(data_5));

AND2 AND2_06(.IN1(addr[5]), .IN2(wr), .OUT(s6));
ram ram_06(.data(data), .wren(s6), .address(1'b1), .clock(clk), .q(data_6));

AND2 AND2_07(.IN1(addr[6]), .IN2(wr), .OUT(s7));
ram ram_07(.data(data), .wren(s7), .address(1'b1), .clock(clk), .q(data_7));

AND2 AND2_08(.IN1(addr[7]), .IN2(wr), .OUT(s8));
ram ram_08(.data(data), .wren(s8), .address(1'b1), .clock(clk), .q(data_8));



AND2 AND2_09(.IN1(addr[8]), .IN2(wr), .OUT(s9));
ram ram_09(.data(data), .wren(s9), .address(1'b1), .clock(clk), .q(data_9));

AND2 AND2_10(.IN1(addr[9]), .IN2(wr), .OUT(s10));
ram ram_10(.data(data), .wren(s10), .address(1'b1), .clock(clk), .q(data_10));

AND2 AND2_11(.IN1(addr[10]), .IN2(wr), .OUT(s11));
ram ram_11(.data(data), .wren(s11), .address(1'b1), .clock(clk), .q(data_11));

AND2 AND2_12(.IN1(addr[11]), .IN2(wr), .OUT(s12));
ram ram_12(.data(data), .wren(s12), .address(1'b1), .clock(clk), .q(data_12));



AND2 AND2_13(.IN1(addr[12]), .IN2(wr), .OUT(s13));
ram ram_13(.data(data), .wren(s13), .address(1'b1), .clock(clk), .q(data_13));

AND2 AND2_14(.IN1(addr[13]), .IN2(wr), .OUT(s14));
ram ram_14(.data(data), .wren(s14), .address(1'b1), .clock(clk), .q(data_14));

AND2 AND2_15(.IN1(addr[14]), .IN2(wr), .OUT(s15));
ram ram_15(.data(data), .wren(s15), .address(1'b1), .clock(clk), .q(data_15));

AND2 AND2_16(.IN1(addr[15]), .IN2(wr), .OUT(s16));
ram ram_16(.data(data), .wren(s16), .address(1'b1), .clock(clk), .q(data_16));

endmodule

module ram_blocks(
    input clk,
    input [15:0]addr,
    input [15:0]data,
    input wr,
    
    output [15:0]data_1,
    output [15:0]data_2,
    output [15:0]data_3,
    output [15:0]data_4,
    output [15:0]data_5,
    output [15:0]data_6,
    output [15:0]data_7,
    output [15:0]data_8,
    output [15:0]data_9,
    output [15:0]data_10,
    output [15:0]data_11,
    output [15:0]data_12,
    output [15:0]data_13,
    output [15:0]data_14,
    output [15:0]data_15,
    output [15:0]data_16);
    
    wire     [15:0]data_out[15:0];
    wire     [16:0]s;
    
    genvar i;
    generate
    for(i = 0; i < 16; i = i + 1)
    begin : ram_generation
        assign s[i] = addr[i] & wr;
        ram     ram_inst(.data(data), .wren(s[i]), .address(1'b1), .clock(clk), .q(data_out[i]));        
    end
    endgenerate

    assign data_1 = data_out[0];
    assign data_2 = data_out[1];
    assign data_3 = data_out[2];
    assign data_4 = data_out[3];
    assign data_5 = data_out[4];
    assign data_6 = data_out[5];
    assign data_7 = data_out[6];
    assign data_8 = data_out[7];
    assign data_9 = data_out[8];
    assign data_10 = data_out[9];
    assign data_11 = data_out[10];
    assign data_12 = data_out[11];
    assign data_13 = data_out[12];
    assign data_14 = data_out[13];
    assign data_15 = data_out[14];
    assign data_16 = data_out[15];
        
endmodule

    wire     w_cs
    reg     dff_out;
    
    always @(posedge clk)
    begin
        dff_out <= cs;
    end
    assign w_cs = dff_out;

# ** Warning: (vsim-3009) [TSCALE] - Module 'ram_blocks' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb/main_inst_tb/mem_block1/ram_blocks1
# Loading work.decoder
# ** Warning: (vsim-3009) [TSCALE] - Module 'decoder' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb/main_inst_tb/mem_block1/decoder1

** Error: (vsim-3601) Iteration limit reached at time 0 ns.

vsim -t 1ns tb

`timescale 1ps / 1ps

`include "altera_mf.v"
`include "main.v"
`include "pll.v"

module tb;
    reg clk;
    wire clk_108MHz;
    
    main main_tb(
        .clk(clk),
        .clk_108MHz(clk_108MHz));
    
    always
        #5 clk = !clk;

    initial
    begin
        clk = 0;
        #10000;    
        $stop;
    end
    
endmodule

transcript on
vlib work
vlog -sv tb.v
vsim -t 1ps tb
add wave /*
quietly radix unsigned
configure wave -timelineunits ns
run -all
wave zoom full