Итак, у меня есть 2 исходных файла! Один - верхнего уровня иерархии и два нижнего уровня иерархии ( смотрите первый прикрепленный файл).
Для начала я хотел просто промоделировать память программ. По идее при изменении адреса там должны изменяться инструкции на выходе. Вот TB для этого:
=====================================================================
ARCHITECTURE behavior OF tb_porg_rom_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT prog_rom
PORT(
address : IN std_logic_vector(9 downto 0);
clk : IN std_logic;
instruction : OUT std_logic_vector(17 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL address : std_logic_vector(9 downto 0) := (others=>'0');
--Outputs
SIGNAL instruction : std_logic_vector(17 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: prog_rom PORT MAP(
address => address,
instruction => instruction,
clk => clk
);
pClock: process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
pProcess: process
begin
address <= "0000001101";
wait until rising_edge(clk);
wait until rising_edge(clk);
address <= "0000001111";
wait until rising_edge(clk);
wait until rising_edge(clk);
address <= "0000010001";
wait until rising_edge(clk);
wait until rising_edge(clk);
address <= "0000111100";
wait until rising_edge(clk);
wait until rising_edge(clk);
address <= "0000010101";
wait until rising_edge(clk);
wait until rising_edge(clk);
wait; -- will wait forever
END PROCESS;
END;
=====================================================================
Результат моделирования во втором прикрепленном файле.
Потом я попробовал промоделировать все 3 компонента в целом:
=====================================================================
ARCHITECTURE behavior OF tb_kcpsm3_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT embedded_kcpsm3
PORT(
in_port : IN std_logic_vector(7 downto 0);
interrupt : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
port_id : OUT std_logic_vector(7 downto 0);
write_strobe : OUT std_logic;
read_strobe : OUT std_logic;
out_port : OUT std_logic_vector(7 downto 0);
interrupt_ack : OUT std_logic
);
END COMPONENT;
COMPONENT kcpsm3
PORT(
instruction : IN std_logic_vector(17 downto 0);
in_port : IN std_logic_vector(7 downto 0);
interrupt : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
address : OUT std_logic_vector(9 downto 0);
port_id : OUT std_logic_vector(7 downto 0);
write_strobe : OUT std_logic;
out_port : OUT std_logic_vector(7 downto 0);
read_strobe : OUT std_logic;
interrupt_ack : OUT std_logic
);
END COMPONENT;
COMPONENT prog_rom
PORT(
address : IN std_logic_vector(9 downto 0);
clk : IN std_logic;
instruction : OUT std_logic_vector(17 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL interrupt : std_logic := '0';
SIGNAL reset : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL in_port : std_logic_vector(7 downto 0) := (others=>'0');
--Outputs
SIGNAL port_id : std_logic_vector(7 downto 0);
SIGNAL write_strobe : std_logic;
SIGNAL read_strobe : std_logic;
SIGNAL out_port : std_logic_vector(7 downto 0);
SIGNAL interrupt_ack : std_logic;
SIGNAL address : std_logic_vector(9 downto 0) := (others=>'0');
SIGNAL instruction : std_logic_vector(17 downto 0) := (others=>'0');
BEGIN
-- Instantiate the Unit Under Test (UUT)
full: embedded_kcpsm3 PORT MAP(
port_id => port_id,
write_strobe => write_strobe,
read_strobe => read_strobe,
out_port => out_port,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => reset,
clk => clk
);
proc: kcpsm3 PORT MAP(
address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => reset,
clk => clk
);
progrom: prog_rom PORT MAP(
address => address,
instruction => instruction,
clk => clk
);
pClock: process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
pProcess: process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait; -- will wait forever
END PROCESS;
END;
====================================================================
Что из этого получилось я хотел прикрепить в третий прикрепленный файл, но он не поместился. Да вобщем-то там и смотреть то нечего - на выходах UUUUUUUUUUUUUUUUU
Не могу промоделировать ядро PicoBlaze!, Может есть у кого TestBench?
Jan 20 2007, 01:33
