CPUCS = 0x10;                 // CLKSPD[1:0]=10, for 48MHz operation
    
     IFCONFIG = (1<<IFCLKSRC) | (0<<s3048MHZ) | (1<<IFCLKOE) | (0<<ASYNC) | (1<<IFCFG1) | (1<<IFCFG0);
 
 // IFCLKSRC=1   , FIFOs executes on internal clk source
 // IFCLKOE=0    , drive IFCLK pin signal at 30MHz
 // IFCLKPOL=0   , Don't invert IFCLK pin signal from internal clk
 // ASYNC=0      , master samples synchronous
 // GSTATE=0     , Don't drive GPIF states out on PORTE[2:0], debug WF
 // IFCFG[1:0]=11, FX2 in slave FIFO mode

 
    SYNCDELAY;
    REVCTL = (1<<DYN_OUT) | (1<<ENH_PKT);
    
    // EP4 is DIR=OUT, TYPE=BULK, SIZE=512, BUF= as is 2x
    SYNCDELAY;
    EP4CFG = (1<<VALID) | (0<<DIR) | (1<<TYPE1) | (0 << TYPE0);    
    
    // EP8 is DIR=IN, TYPE=BULK, SIZE=512, BUF= as is 2x
    SYNCDELAY;
    EP8CFG = (1<<VALID) | (1<<DIR) | (1<<TYPE1) | (0 << TYPE0);    
 // EP2, EP6 off
     SYNCDELAY;              
     EP2CFG = (0<<VALID) | (0<<DIR) | (1<<TYPE1) | (0 << TYPE0);
 SYNCDELAY;              
     EP6CFG = (0<<VALID)  | (1<<DIR) | (1<<TYPE1) | (0 << TYPE0);
 
 // reset fifo 4 times
    for (i = 0; i < 4; i++)
    {
   SYNCDELAY;
   FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions
   SYNCDELAY;    
   FIFORESET = 0x02;             // reset, FIFO 2
   SYNCDELAY;                    //
   FIFORESET = 0x04;             // reset, FIFO 4
   SYNCDELAY;                    //
   FIFORESET = 0x06;             // reset, FIFO 6
   SYNCDELAY;                    //
   FIFORESET = 0x08;             // reset, FIFO 8
   SYNCDELAY;                    //
   FIFORESET = 0x00;             // deactivate NAK-ALL
    }
    
    SYNCDELAY;
    PINFLAGSAB = 0xD9;  // FLAGA - fixed EP4EF, FLAGB - fixed EP4FF
    // FLAGC - fixed EP8FF, FLAGD - n.u.
     SYNCDELAY;
    PINFLAGSCD = 0x0F;
     
    SYNCDELAY;
    PORTACFG = (0<<FLAGD) | (0<<SLCS);          // FLAGD, set alt. func. of PA7 pin
     
    SYNCDELAY;
     FIFOPINPOLAR = 0x00;          // all signals active low
     
 // use auto out mode
    SYNCDELAY;
    EP4FIFOCFG = 0x00;            // AUTOOUT=0, WORDWIDE=1
    
    // EP4 fifo is AUTOOUT=1, AUTOIN=0, ZEROLEN=0, WORDWIDE=1
    SYNCDELAY;
    EP4FIFOCFG = (0<<INFM1) | (0<<OEP1) | (1<<AUTOOUT) | (0<<AUTOIN) | (0<<ZEROLENIN) | (0<<WORDWIDE);    // 8 bit

 
   // use auto in mode
    SYNCDELAY;
    EP8FIFOCFG = 0x00;

    // AUTOIN=1, ZEROLENIN=1, WORDWIDE=0
     SYNCDELAY;
    EP8FIFOCFG = (0<<INFM1) | (0<<OEP1) | (0<<AUTOOUT) | (1<<AUTOIN) | (1<<ZEROLENIN) | (0<<WORDWIDE);
     
    SYNCDELAY;
    EP8AUTOINLENH = 0x02; // Auto-commit 512-byte packets
    SYNCDELAY;
    EP8AUTOINLENL = 0x00;

     
       mov     PacketSizeLow,#0x00
       mov     PacketSizeHigh,#0x02
       mov     dptr,#USBCS      ; bit7 - Mode jf PLL  (480/12)  
       movx    a,@dptr
       ANL     a,#10000000b
     JNZ     PLL480             ; branch if HCM != 0

       mov     PacketSizeLow,#0x40
       mov     PacketSizeHigh,#0x00
     PLL480:    
      _nop
       WriteX  #EP8AUTOINLENH,PacketSizeHigh;
      _nop
       WriteX  #EP8AUTOINLENL,PacketSizeLow;

BOOL DR_SetConfiguration( void )  
{ // Called when a Set Configuration command is received
 
 if( EZUSB_HIGHSPEED( ) )
 { // ...FX2 in high speed mode
   SYNCDELAY;
   EP8AUTOINLENH = 0x02;   // set core AUTO commit len = 512 bytes
   SYNCDELAY;
   EP8AUTOINLENL = 0x00;
 }
 else
 { // ...FX2 in full speed mode
   SYNCDELAY;
   EP8AUTOINLENH = 0x00;   // set core AUTO commit len = 64 bytes
   SYNCDELAY;
   EP8AUTOINLENL = 0x40;
 }
     
 Configuration = SETUPDAT[ 2 ];
 return( TRUE );        // Handled by user code
}

Get PipeInfo
Interface Size 136
Pipe:  0   Type: BLK Endpoint:  1 OUT  MaxPktSize: 0x200
Pipe:  1   Type: BLK Endpoint:  1 IN   MaxPktSize: 0x200
Pipe:  2   Type: BLK Endpoint:  2 OUT  MaxPktSize: 0x200
Pipe:  3   Type: BLK Endpoint:  4 OUT  MaxPktSize: 0x200
Pipe:  4   Type: BLK Endpoint:  6 IN   MaxPktSize: 0x200
Pipe:  5   Type: BLK Endpoint:  8 IN   MaxPktSize: 0x200

Get PipeInfo
Interface Size 136

Pipe:  0   Type: BLK Endpoint:  1 OUT  MaxPktSize: 0x40
Pipe:  1   Type: BLK Endpoint:  1 IN   MaxPktSize: 0x40
Pipe:  2   Type: BLK Endpoint:  2 OUT  MaxPktSize: 0x40
Pipe:  3   Type: BLK Endpoint:  4 OUT  MaxPktSize: 0x40
Pipe:  4   Type: BLK Endpoint:  6 IN   MaxPktSize: 0x40
Pipe:  5   Type: BLK Endpoint:  8 IN   MaxPktSize: 0x40