typedef struct _AT91S_PMC {
    AT91_REG     PMC_SCER;     // System Clock Enable Register
    AT91_REG     PMC_SCDR;     // System Clock Disable Register
    AT91_REG     PMC_SCSR;     // System Clock Status Register
    AT91_REG     Reserved0[1];     //
    AT91_REG     PMC_PCER;     // Peripheral Clock Enable Register
    AT91_REG     PMC_PCDR;     // Peripheral Clock Disable Register
    AT91_REG     PMC_PCSR;     // Peripheral Clock Status Register
    AT91_REG     Reserved1[1];     //
    AT91_REG     PMC_MOR;     // Main Oscillator Register
    AT91_REG     PMC_MCFR;     // Main Clock  Frequency Register
    AT91_REG     Reserved2[1];     //
    AT91_REG     PMC_PLLR;     // PLL Register
    AT91_REG     PMC_MCKR;     // Master Clock Register
    AT91_REG     Reserved3[3];     //
    AT91_REG     PMC_PCKR[3];     // Programmable Clock Register
    AT91_REG     Reserved4[5];     //
    AT91_REG     PMC_IER;     // Interrupt Enable Register
    AT91_REG     PMC_IDR;     // Interrupt Disable Register
    AT91_REG     PMC_SR;     // Status Register
    AT91_REG     PMC_IMR;     // Interrupt Mask Register
} AT91S_PMC, *AT91PS_PMC;

#define AT91C_BASE_PMC       ((AT91PS_PMC)     0xFFFFFC00) // (PMC) Base Address

    AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UDP;

__inline unsigned int AT91F_AIC_ConfigureIt (
    AT91PS_AIC pAic,  // \arg pointer to the AIC registers
    unsigned int irq_id,     // \arg interrupt number to initialize
    unsigned int priority,   // \arg priority to give to the interrupt
    unsigned int src_type,   // \arg activation and sense of activation
    void (*newHandler) () ) // \arg address of the interrupt handler
{
    unsigned int oldHandler;
    unsigned int mask;

    oldHandler = pAic->AIC_SVR[irq_id];

    mask = 0x1 << irq_id;
    //* Disable the interrupt on the interrupt controller
    pAic->AIC_IDCR = mask;
    //* Save the interrupt handler routine pointer and the interrupt priority
    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler;
    //* Store the Source Mode Register
    pAic->AIC_SMR[irq_id] = src_type | priority;
    //* Clear the interrupt on the interrupt controller
    pAic->AIC_ICCR = mask;

    return oldHandler;
}

pAic->AIC_IDCR = mask;

typedef struct _AT91S_AIC {
    AT91_REG     AIC_SMR[32];     // Source Mode Register
    AT91_REG     AIC_SVR[32];     // Source Vector Register
    AT91_REG     AIC_IVR;     // IRQ Vector Register
    AT91_REG     AIC_FVR;     // FIQ Vector Register
    AT91_REG     AIC_ISR;     // Interrupt Status Register
    AT91_REG     AIC_IPR;     // Interrupt Pending Register
    AT91_REG     AIC_IMR;     // Interrupt Mask Register
    AT91_REG     AIC_CISR;     // Core Interrupt Status Register
    AT91_REG     Reserved0[2];     //
    AT91_REG     AIC_IECR;     // Interrupt Enable Command Register
    AT91_REG     AIC_IDCR;     // Interrupt Disable Command Register
    AT91_REG     AIC_ICCR;     // Interrupt Clear Command Register
    AT91_REG     AIC_ISCR;     // Interrupt Set Command Register
    AT91_REG     AIC_EOICR;     // End of Interrupt Command Register
    AT91_REG     AIC_SPU;     // Spurious Vector Register
    AT91_REG     AIC_DCR;     // Debug Control Register (Protect)
    AT91_REG     Reserved1[1];     //
    AT91_REG     AIC_FFER;     // Fast Forcing Enable Register
    AT91_REG     AIC_FFDR;     // Fast Forcing Disable Register
    AT91_REG     AIC_FFSR;     // Fast Forcing Status Register
} AT91S_AIC, *AT91PS_AIC;

AT91F_PITInit(PIT, mck, 1000)

#define PIT_HZ    1000

AT91C_BASE_PITC->PITC_PIMR = AT91C_PITC_PITEN | AT91C_PITC_PITIEN | ((mck + PIT_HZ * 8) / (PIT_HZ * 16) - 1);