//---------------------------------------------------------------------------
// Initialize the PHY chip
// Performs the following steps:
// 1.Determines PHY address
// 2.Resets PHY
// 3.Sets PHY clock
// 4.Sets Line speed (auto-negotiation if selected)
//---------------------------------------------------------------------------
int init_phy(void)
{
bint phy_reg;

MCFG = MCFG_HCLK_DIV_28|MCFG_RESET_MII_MGMT;
vSmartDelay_ms( 2 );

#if( EMAC_CFG_RMII == 0 )
MCOMMAND &= ~CR_RMII;
#else
MCOMMAND |= CR_RMII;
#if defined __IOLPC2458_H
SUPP = SUPP_RESET_MII;
#else
SUPP = 0; // Assume and configure RMII link speed logic for 10Mbit
#endif
#endif

for( int i = 0; i < 7; i++ )
{ // Check dividers to yield MII frequency ~2.5 MHz
if( ( (configCPU_CLOCK_HZ/100000L)/mii_dividers[i][0] ) <= 25 )
{ // Index [i][0] = decimal div value, [i][1] = MCFG reg val
MCFG = mii_dividers[i][1]; // Remove reset, set proper MIIM divider
break;
}
}
vSmartDelay_ms( 10 ); // Short delay while PHY exits reset and new divider is set

for( phy_addr = 0; phy_addr < 32; phy_addr++ )
{ // Put PHY in reset mode
write_PHY( PHY_REG_BMCR, BMCR_RESET );
// Wait for hardware reset to end
for( int i = 0; i < 128; i++ )
{ vSmartDelay_ms( 1 );
if( !(read_PHY( PHY_REG_BMCR ) & BMCR_RESET) )
{ // Reset complete
goto phy_found;
}
}
}
printst( "PHY:None" );
return( 1 );

phy_found:
{
// Check if this is a valid PHY
ulong id_phy = (read_PHY( PHY_REG_IDR1 )<<16)|read_PHY( PHY_REG_IDR2 );
if( id_phy == KS8721BL_ID )
xprintf( "PHY%02u:KS8721BL ", phy_addr );
else
{ xprintf( "PHY%02u:%08X ", phy_addr, id_phy );
return( 2 );
}
}

..........





void write_PHY( bint phyreg, bint value )
{
MADR = (phy_addr<<8) | phyreg;
MWTD = value;
// Wait utill operation completed
for( int tout = 0; tout < MII_WR_TOUT; tout++ )
{
if( ( MIND & MIND_BUSY ) == 0 )
break;
}
}

bint read_PHY( bint phyreg )
{
MADR = (phy_addr<<8) | phyreg;
MCMD = MCMD_READ;

// Wait until operation completed
for( int tout = 0; tout < MII_RD_TOUT; tout++ )
{ if( (MIND & (MIND_BUSY|MIND_NOT_VALID) ) == 0 )
{ MCMD = 0;
return( MRDD );
}
}
return( 0 );
}