//---------------------------------------------------------------------------
// Initialize the PHY chip
// Performs the following steps:
// 1.Determines PHY address
// 2.Resets PHY
// 3.Sets PHY clock
// 4.Sets Line speed (auto-negotiation if selected)
//---------------------------------------------------------------------------
int init_phy(void)
{
bint phy_reg;

MCFG = MCFG_HCLK_DIV_28|MCFG_RESET_MII_MGMT;
vSmartDelay_ms( 2 );

#if( EMAC_CFG_RMII == 0 )
MCOMMAND &= ~CR_RMII;
#else
MCOMMAND |= CR_RMII;
#if defined __IOLPC2458_H
SUPP = SUPP_RESET_MII;
#else
SUPP = 0; // Assume and configure RMII link speed logic for 10Mbit
#endif
#endif

for( int i = 0; i < 7; i++ )
{ // Check dividers to yield MII frequency ~2.5 MHz
if( ( (configCPU_CLOCK_HZ/100000L)/mii_dividers[i][0] ) <= 25 )
{ // Index [i][0] = decimal div value, [i][1] = MCFG reg val
MCFG = mii_dividers[i][1]; // Remove reset, set proper MIIM divider
break;
}
}
vSmartDelay_ms( 10 ); // Short delay while PHY exits reset and new divider is set

for( phy_addr = 0; phy_addr < 32; phy_addr++ )
{ // Put PHY in reset mode
write_PHY( PHY_REG_BMCR, BMCR_RESET );
// Wait for hardware reset to end
for( int i = 0; i < 128; i++ )
{ vSmartDelay_ms( 1 );
if( !(read_PHY( PHY_REG_BMCR ) & BMCR_RESET) )
{ // Reset complete
goto phy_found;
}
}
}
printst( "PHY:None" );
return( 1 );

phy_found:
{
// Check if this is a valid PHY
ulong id_phy = (read_PHY( PHY_REG_IDR1 )<<16)|read_PHY( PHY_REG_IDR2 );
if( id_phy == KS8721BL_ID )
xprintf( "PHY%02u:KS8721BL ", phy_addr );
else
{ xprintf( "PHY%02u:%08X ", phy_addr, id_phy );
return( 2 );
}
}

..........





void write_PHY( bint phyreg, bint value )
{
MADR = (phy_addr<<8) | phyreg;
MWTD = value;
// Wait utill operation completed
for( int tout = 0; tout < MII_WR_TOUT; tout++ )
{
if( ( MIND & MIND_BUSY ) == 0 )
break;
}
}

bint read_PHY( bint phyreg )
{
MADR = (phy_addr<<8) | phyreg;
MCMD = MCMD_READ;

// Wait until operation completed
for( int tout = 0; tout < MII_RD_TOUT; tout++ )
{ if( (MIND & (MIND_BUSY|MIND_NOT_VALID) ) == 0 )
{ MCMD = 0;
return( MRDD );
}
}
return( 0 );
}

MAC_MCFG = MCFG_HCLK_DIV_28;

  /* Initialize MAC control registers. */
  MAC_MAC1 = MAC1_PASS_ALL;
  MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
  MAC_MAXF = ETH_MAX_FLEN;
  MAC_CLRT = CLRT_DEF;
  MAC_IPGR = IPGR_DEF;

#define MCFG_HCLK_DIV_28      (7 << 2)

int init_phy(void)
{
    MCFG = MCFG_HCLK_DIV_28|MCFG_RESET_MII_MGMT;
      vSmartDelay_ms( 2 );

#if( EMAC_CFG_RMII == 0 )
    MCOMMAND &= ~CR_RMII;
#else
    MCOMMAND |= CR_RMII;
#if defined __IOLPC2458_H
    SUPP = SUPP_RESET_MII;
#else
    SUPP = 0;                 // Assume and configure RMII link speed logic for 10Mbit
#endif
#endif

    for( int i = 0; i < 7; i++ )
    {    // Check dividers to yield MII frequency ~2.5 MHz
        if( ( (configCPU_CLOCK_HZ/100000L)/mii_dividers[i][0] ) <=  25 )
        {    MCFG = mii_dividers[i][1];        // Remove reset, set proper MIIM divider
            break;
        }
    }
    vSmartDelay_ms( 10 );    // Short delay while PHY exits reset and new divider is set

      for( phy_addr = 1; phy_addr <= 31; phy_addr++ )
      {   // Put PHY in reset mode
        write_PHY( PHY_REG_BMCR, BMCR_RESET );
        // Wait for hardware reset to end
        for( int i = 0; i < 128; i++ )
        {   vSmartDelay_ms( 1 );
            if( !(read_PHY( PHY_REG_BMCR ) & BMCR_RESET) )
            {    // Reset complete
                goto phy_found;
              }
        }
    }
    printst( "PHY:Missing " );
    return( 1 );

phy_found:
    {
    // Check if this is a valid PHY
      ulong id_phy = (read_PHY( PHY_REG_IDR1 )<<16)|read_PHY( PHY_REG_IDR2 );
    if( id_phy == KS8721BL_ID  )
        xprintf( "PHY%2X:KS8721BL ", phy_addr );
    else if( id_phy == KS8041TL_ID  )
        xprintf( "PHY%2X:KS8041TL ", phy_addr );
    else
    {    xprintf( "PHY%2X:%8X -Unknown ", phy_addr, id_phy );
         return( 2 );
    }
    }

      // Sanity check...
...........

#define DEFAULT_PHY_ADDR (1)
  
    for( phy_addr = DEFAULT_PHY_ADDR;; )
      {   // Put PHY in reset mode
        write_PHY( PHY_REG_BMCR, BMCR_RESET );
        // Wait for hardware reset to end
        for( int i = 0; i < 128; i++ )
        {   vSmartDelay_ms( 1 );
            if( !(read_PHY( PHY_REG_BMCR ) & BMCR_RESET) )
            {    // Reset complete
                goto phy_found;
              }
        }
        phy_addr = ( phy_addr + 1 ) & 0x1F;
        if( phy_addr == DEFAULT_PHY_ADDR )
                           {    printst( "PHY:Missing " );
                                 return( 1 );
        }
        
    }

    for (phy_addr = 1; phy_addr <= 31; phy_addr++)
        // Put PHY in reset mode
        write_PHY(PHY_REG_BMCR, BMCR_RESET);

    phy_addr = 1;

    for (int i = 0; i < 128; i++) {  
        if (!(read_PHY( PHY_REG_BMCR ) & BMCR_RESET))
            // Reset complete
            goto phy_found;
        vSmartDelay_ms(1);
    }
    
    for (phy_addr = 2; phy_addr <= 31; phy_addr++) {
        if (!(read_PHY(PHY_REG_BMCR) & BMCR_RESET))
            goto phy_found;
    }
    
    printst("PHY:Missing ");
    return (1);
      
phy_found: