cd D:/Tmp/23
# reading C:\modeltech_6.5b\win32/../modelsim.ini
do D:/Tmp/23/compile.do
# Copying C:\modeltech_6.5b\win32/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied C:\modeltech_6.5b\win32/../modelsim.ini to modelsim.ini.
# Updated modelsim.ini.
# -- Compiling module cache
# -- Compiling module memory
# -- Compiling module proc
#
# Top level modules:
# cache
# memory
# proc
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling package std_logic_util
# -- Compiling package body std_logic_util
# -- Loading package std_logic_util
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_util
# -- Compiling entity cache_set
# -- Compiling architecture only of cache_set
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity top
# -- Compiling architecture only of top
vsim work.top
# vsim work.top
# ** Note: (vsim-3812) Design is being optimized...
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading work.top(only)#1
# Loading work.proc(fast)
# Loading work.cache(fast)
# Loading work.std_logic_util(body)
# Loading work.cache_set(only)#1
# Loading work.memory(fast)
run 100ns
# 20: Starting Read/Write test
# 20: Writing data=0000 to addr=00
# 60: Write miss, picking set 3
run -all
# 220: Writing data=0001 to addr=01
# 260: Write miss, picking set 3
# 420: Writing data=0002 to addr=02
# 460: Write miss, picking set 3
# 620: Writing data=0003 to addr=03
# 660: Write miss, picking set 3
# 820: Writing data=0004 to addr=04
# 860: Write miss, picking set 3
# 1020: Writing data=0005 to addr=05
# 1060: Write miss, picking set 3
# 1220: Writing data=0006 to addr=06
# 1260: Write miss, picking set 3
# 1420: Writing data=0007 to addr=07
# 1460: Write miss, picking set 3
# 1620: Writing data=0008 to addr=08
# 1660: Write miss, picking set 3
# 1820: Writing data=0009 to addr=09
# 1860: Write miss, picking set 3
# 2020: Reading from addr=00
# 2060: Read hit to set 3
# 2100: Reading from addr=01
# 2140: Read hit to set 3
# 2180: Reading from addr=02
# 2220: Read hit to set 3
# 2260: Reading from addr=03
# 2300: Read hit to set 3
# 2340: Reading from addr=04
# 2380: Read hit to set 3
# 2420: Reading from addr=05
# 2460: Read hit to set 3
# 2500: Reading from addr=06
# 2540: Read hit to set 3
# 2580: Reading from addr=07
# 2620: Read hit to set 3
# 2660: Reading from addr=08
# 2700: Read hit to set 3
# 2740: Reading from addr=09
# 2780: Read hit to set 3
# Read/Write test done
# ** Note: $stop : proc.v(75)
# Time: 2820 ns Iteration: 0 Instance: /top/p
# Break at proc.v line 75

module countbit(
        input clk,             //такт...
        input [7:0] data,      //данные
        input load,            //загрузка данных
        output reg fin,        //флаг, счет закончен
        output reg [4:0] count //результат
        );
        
    bit [7:0] tempbuff;
        
    always @ (posedge clk or posedge load) begin    
      if(load) begin
        tempbuff <= data;
        fin <= 0;
        count <= 0;
      end
     else begin
        if(tempbuff[0]) begin
          tempbuff <= tempbuff >> 1;
          count++;
        end
      else fin <= 1;    
     end
   end
endmodule        

module test;
  bit clk;
  bit [7:0] data;
  bit load;
  bit fin;
  bit [4:0] count;

    initial begin
     clk = 0;
     data = 0;
     load = 0;

    #5 data = 8'b11001111;
    #5 load = 1;
    #2 load = 0;
    wait(fin == 1); //Ждать пока счет не закончен
    
    #5 data = 8'b10101011;
    #5 load =1;
    #2 load = 0;
    wait(fin == 1); //Ждать пока счет не закончен
    #5 $stop;
    end
    
    always #2 clk = ~clk;
    
countbit P1 (
   .clk(clk),
   .data(data),
   .load(load),
   .fin(fin),
   .count(count)
  );
endmodule