этот бит взводит функция alt_avalon_sgdma_construct_mem_to_stream_desc()
Цитата
This function constructs a single SG-DMA descriptor in the memory specified in
alt_avalon_sgdma-descriptor *desc for an Avalon-MM to Avalon-ST transfer. The
destination (write) data for the transfer goes to the Avalon-ST interface connected to the SG-DMA
controller's streaming write port. The function sets the OWNED_BY_HW bit in the descriptor's control
field, marking the completed descriptor as ready to run. The descriptor is processed when the
SG-DMA controller receives the descriptor and the RUN bit is 1.
пожалуй, плохая идея вызывать функцию так
Код
alt_avalon_sgdma_construct_mem_to_stream_desc(
(alt_sgdma_descriptor *) desc, // descriptor I want to work with
(alt_sgdma_descriptor *) desc,// pointer to "next"
(alt_u32 *) ActualData, // starting read address
(length), // # bytes
0, // don't read from constant address
1, // generate sop
1, // generate endofpacket signal
0); // atlantic channel (don't know/don't care: set to 0)
указатель на "next" д.б. другим (нужен еще один дескриптор).
вот почему:
Цитата
The function sets the OWNED_BY_HW bit in the descriptor's control field, marking the completed
descriptor as ready to run. The descriptor is processed when the SG-DMA controller receives the
descriptor and the RUN bit is 1.
The next field of the descriptor being constructed is set to the address in *next. The
OWNED_BY_HW bit of the descriptor at *next is explicitly cleared. Once the SG-DMA completes
processing of the *desc, it does not process the descriptor at *next until its OWNED_BY_HW bit is
set. To create a descriptor chain, you can repeatedly call this function using the previous call's
*next pointer in the *desc parameter.
OWNED_BY_HW =1 значит, что дескриптор готов к обработке устройством и можно вызывать, например, alt_avalon_sgdma_do_sync_transfer(). второй дескриптор смысловой нагрузки не несет, затычка, но память под него выделить надо.
Цитата
This bit determines whether hardware or software has write access
to the current register.
When this bit is set to 1, the core can update the descriptor and
software should not access the descriptor due to the possibility of
race conditions. Otherwise, it is safe for software to update the
descriptor.
Ethernet + Cyclone + Nios
Nov 26 2009, 10:05
