module lcell_xor
(
input  in_strob,
output out_a,
output out_b
);

wire   out_lcell[5:0];

lcell     lcell_a  (
                   .in         (in_strob),
                   .out        (out_lcell[0])
                   );

genvar i;
    generate for (i = 1; i <= 5; i = i + 1)
        begin : block
lcell    lcell_b  (
                   .in         (out_lcell[i-1]),
                   .out        (out_lcell[i])
                   );    
        end
    endgenerate

assign out_a = out_lcell[1] ^ out_lcell[5];
assign out_b = (out_lcell[2] != out_lcell[4]);

endmodule

wire clk = clkout_from_pll_in_zero_buffer_mode;

always_ff @(posedge clk) begin
  // IO register latch
  a_reg   <= a;
  d_reg   <= d;
  nrd_reg <= nrd;
  nwr_reg <= nwr;
  ncs_reg <= ncs;
  //
  write   <= ~nwr_reg & ~write & ~ncs_reg;
end

always_ff @(posedge clk) begin
  if (write) begin
    case (a_reg)
      // bla-bla-bla
    endcase
  end
end

    type state_t is (
        st_idle,
        st_setup_1,
        st_setup_2,
        st_write_1,
        st_write_2,
        st_hold
    );
    
    signal state : state_t;

          
    
begin

    RD <= '0';

    
    process(reset, clk)
    begin
        if (reset='1') then
            state <= st_idle;
            CS_out <= '1';
            AD_out <= '0';
            nWE_out <= '1';
            ready <= '0';
        elsif rising_edge(clk) then
            AD_out <= '1';
            ready <= '0';
            CS_out <= '1';
            case state is
                when st_idle =>
                    if cmd_write='1' then
                        state <= st_setup_1;
                    else
                        AD_out <= '0';
                        ready <= '1';
                    end if;
                when st_setup_1 =>
                    state <= st_setup_2;
                when st_setup_2 =>
                    state <= st_write_1;
                when st_write_1 =>
                    CS_out <= '0';
                    state <= st_write_2;
                when st_write_2 =>
                    CS_out <= '0';
                    state <= st_hold;
                when st_hold =>
                    ready <= '1';
                    state <= st_idle;
            end case;
        end if;
    end process;