`define VAR1

module tq(
  input         clk_i,
  input         rst_i,
  input  [15:0] in_i,
  output [3:0]  out_o
);

logic [15:0] in;
logic [3:0]  out;

always_ff @(posedge clk_i, posedge rst_i)
  if(rst_i)
    in <= '0;
  else
    in <= in_i;  


`ifdef VAR1

always_comb
  begin
    out = 4'b0000;
    casex (in)
        16'bxxxxxxxxxxxxxxx1: out = 4'b0000;
        16'bxxxxxxxxxxxxxx10: out = 4'b0001;
        16'bxxxxxxxxxxxxx100: out = 4'b0010;
        16'bxxxxxxxxxxxx1000: out = 4'b0011;
        16'bxxxxxxxxxxx10000: out = 4'b0100;
        16'bxxxxxxxxxx100000: out = 4'b0101;
        16'bxxxxxxxxx1000000: out = 4'b0110;
        16'bxxxxxxxx10000000: out = 4'b0111;
        16'bxxxxxxx100000000: out = 4'b1000;
        16'bxxxxxx1000000000: out = 4'b1001;
        16'bxxxxx10000000000: out = 4'b1010;
        16'bxxxx100000000000: out = 4'b1011;
        16'bxxx1000000000000: out = 4'b1100;
        16'bxx10000000000000: out = 4'b1101;
        16'bx100000000000000: out = 4'b1110;
        16'b1000000000000000: out = 4'b1111;
    endcase
  end
  
`else

always_comb
  begin
    out = 4'b0000;
    for(int i = 15; i>=0; i--)
      if(in[i])
        out = i;    
  end
  
`endif


always_ff @(posedge clk_i, posedge rst_i)
  if(rst_i)
    out_o <= '0;
  else
    out_o <= out;  


endmodule