module 5584AP6(input wire ez_n, input wire sed, inout wire [7:0] A, inout wire [7:0] B);

assign A = !ez_n && !sed ? B : 8'hzz;
assign B = !ez_n &&  sed ? A : 8'hzz;

endmodule

module bus(e1,e2,a,y);
    input e1,e2;
    inout a,y;
reg a1,y1;
    always @(e1 or e2)
        begin
case ({e1,e2})
                    'b00:
                    begin
                        y1=a;
                        a1=y;
                    end
                         'b01:
                    begin
                        y1=a;
                        a1='bz;
                    end
                    'b10:
                    begin
                        y1='bz;
                        a1=y;
                    end
                    'b11:
                    begin
                        y1='bz;
                        a1='bz;
                    end    
                    endcase
            end
                assign y=y1;
                assign a=a1;
endmodule  

module tb;
    reg y2,a2;
    reg e11,e22;    
    
    bus b(e11,e22,a2,y2);
    initial begin
    e11='b0;e22='b1;
    forever begin # 20 e11=~e11; e22=~e22; end
    end                                        
    
    initial
        begin y2='b0;
            a2='b1;
            forever begin # 2 y2=~y2; a2=~a2; end
        end    
        
    initial #200 $finish;
    endmodule