// Initialize main oscillator
    AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN;
    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));

    // Initialize PLL at 96MHz (96.109) and USB clock to 48MHz
    //18432000Hz / 14 * (72+1) = 96109714MHz
  
    AT91C_BASE_PMC->PMC_PLLR = BOARD_USBDIV | BOARD_CKGR_PLL | BOARD_PLLCOUNT
                               | BOARD_MUL | BOARD_DIV;
    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK));

    // Wait for the master clock if it was already initialized
    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));

    // Switch to slow clock + prescaler
    AT91C_BASE_PMC->PMC_MCKR = BOARD_PRESCALER; //2
    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));

unsigned int over=0;
unsigned int mas[1000];
unsigned char count=0;
static void ISR_TC2(void)
{
   unsigned int uiSR = AT91C_BASE_TC2->TC_SR;
    if( (uiSR & AT91C_TC_COVFS) )
   {
       over++;
   }
   if( (uiSR & AT91C_TC_LDRAS) )
   {
       mas[count] = AT91C_BASE_TC2->TC_RA;
       count++;
       over=0;
   }
  
    
}
void InitTC()
{
  
    //AIC configure.
    AT91C_BASE_AIC->AIC_IDCR = 1 << AT91C_ID_TC2;     // Disable the interrupt first
    AT91C_BASE_AIC->AIC_SMR[AT91C_ID_TC2] = 0;
    AT91C_BASE_AIC->AIC_SVR[AT91C_ID_TC2] = (unsigned int) ISR_TC2;
    AT91C_BASE_AIC->AIC_ICCR = 1 << AT91C_ID_TC2;     // Clear interrupt
    AT91C_BASE_AIC->AIC_IECR = 1 << AT91C_ID_TC2;     // Enables interrupts
    
  
    
    // Enable PWMC peripheral clock
    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_TC2;
    
    // Disable TC clock
    AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS;

    // Disable interrupts
    AT91C_BASE_TC2->TC_IDR = 0xFFFFFFFF;

    // Clear status register
    AT91C_BASE_TC2->TC_SR;

    // Set mode
    AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | // MCK/2
                             AT91C_TC_BURST_NONE |
                             AT91C_TC_EEVTEDG_RISING |//AT91C_TC_EEVTEDG_BOTH |
                             AT91C_TC_ABETRG |    
                             AT91C_TC_LDRA_RISING;//AT91C_TC_LDRA_BOTH; // each edge of TIOA
    // Enable interrpt
    AT91C_BASE_TC2->TC_IER = AT91C_TC_COVFS | // Counter Overflow
                             AT91C_TC_LDRAS;  // RA Loading
    
    // Start TC2  
    AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
    
     // connect to PIO for TIOA2
    AT91C_BASE_PIOA->PIO_BSR= AT91C_PA26_TIOA2;
    AT91C_BASE_PIOA->PIO_PDR = AT91C_PA26_TIOA2;
}

                RA    OVER    0xFFFF        MCK                ms                Fre
PLL    max    22149    7    65536    480901    48054857    20,01466782    49,96335732
PLL    min    21561    7    65536    480313    48054857    19,99019579    50,02452255
Main O    min    53131    2    65536    184203    18432000    19,98730469    50,03175844
Main O    max    53235    2    65536    184307    18432000    19,99858941    50,00352672