type Ara is array (NATURAL RANGE <>) of std_logic_vector (Input_Bits-1 downto 0);
constant InP: Ara:=("011111","000111","000001","101000",..............................,"000000");

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ROM is
port (CLK : in std_logic;
EN : in std_logic;
ADDR : in std_logic_vector(15 downto 0);
DATA : out std_logic_vector(31 downto 0));
end ROM;

architecture syn of ROM is





type rom_type is array (0 to 1007) of std_logic_vector (31 downto 0);
signal ROM : rom_type:= (


X"00000000", X"00040050", X"000d00c0", X"00cc01f0", X"00ea0180", X"01bb0080", X"01aa0090", X"01720120",
X"014d0100", X"011001f1", X"010a00c1", X"00000010", X"00110160", X"00710200", X"00810110", X"008901a0",
X"008d0111", X"00b801e0", X"00c10112", X"01cb0230", X"016c0091", X"015a0150", X"00000020", X"00130181",
X"004d0210", X"006800c2", X"006c0140", X"00cc0092", X"01e401d0", X"01c00130", X"01a201e1", X"01630093",
X"01200141", X"00000030", X"001200d0", X"001901c0", X"00620231", X"00680211", X"007800a0", X"009d0142",
X"00ad00f0", X"01d401c1", X"01b30220", X"01740190", X"00000040", X"00120212", X"00310131", X"00550170",
X"009b0221", X"00bd00d1", X"00e300a1", X"01400232", X"012b0041", X"012d0070", X"01220171", X"00000051"

-- и так далее

);
attribute ROM_STYLE : string; ---атрибуты для того чтобы при синтезе распределение было в блоковую память
attribute ROM_STYLE of ROM: signal is "block";

begin



process (CLK)
begin
if (CLK'event and CLK = '1') then
if (EN = '1') then
DATA <= ROM(conv_integer(ADDR));
end if;
end if;
end process;

end syn;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

library synplify;


entity ROM is
port (CLK : in std_logic;
EN : in std_logic;
ADDR : in std_logic_vector(6 downto 0);
DATA : out std_logic_vector(6-1 downto 0));
end ROM;

architecture syn of ROM is

-- mem is the signal that defines the RAM

type MEM is array (0 to 127) of std_logic_vector (6-1 downto 0);

signal ROM : MEM:=("000000",.................,"000000");

attribute syn_ramstyle : string;
attribute syn_ramstyle of ROM : signal is "block_ram";

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ram32_16 is
port (WAddress, RAddress:in std_logic_vector(4 downto 0);
Data : in std_logic_vector (15 downto 0);
WClock, RClock,WE,RE:in std_logic;
Q :out std_logic_vector (15 downto 0));
end ram32_16;

architecture rtl of ram32_16 is
component ram
port (Data : in std_logic_vector (15 downto 0);
WE : in std_logic;
RE : in std_logic;
WClock : in std_logic;
RClock : in std_logic;
WAddress : in std_logic_vector (4 downto 0);
RAddress : in std_logic_vector (4 downto 0);
Q:  out std_logic_vector (15 downto 0)
);
end component;
begin
R_32_16: ram
port map (Data => Data,
WE => WE,
WAddress => WAddress,
RE => RE,
RAddress => RAddress,
WClock => WClock,
RClock => RClock,
Q => Q);
end rtl;
-- RAM.vhd

type mem_type is array (DATA_DEPTH downto 0) of std_logic_vector (7 downto 0);
    signal mem: mem_type;

    attribute syn_ramstyle : string;
    attribute syn_ramstyle of mem : signal is [b]"no_rw_check"[/b];