void TD_Init(void)             // Called once at startup
{
/*  OLD
*/
   BREAKPT &= ~bmBPEN;      // to see BKPT LED go out TGE
   Rwuen = TRUE;            // Enable remote-wakeup


/*
   my code
*/

    CPUCS = 0x10;  // 48 MHz

  SYNCDELAY;
  PINFLAGSAB = 0xF0;            // FLAGA - indexed, FLAGB - EP8FF
  SYNCDELAY;
  PINFLAGSCD = 0x08;            // FLAGC - EP2EF, FLAGD - indexed
  SYNCDELAY;

  FIFOPINPOLAR = 0x00;

  SYNCDELAY;                    //
  PORTACFG = 0x40;  // FLAGD is /CHIPSELECT


////////////  STEP 1 TRM

  SYNCDELAY;                    //
  IFCONFIG = 0xC8; // for async

////////////  STEP 2 TRM

  SYNCDELAY;                    //
  IFCONFIG |= 0x03; // enable slave FIFO

////////////  STEP 3 TRM

  SYNCDELAY;                    //
  REVCTL=0x03;

////////////  STEP 4 TRM

  // EP2 512 BULK OUT 2x
  SYNCDELAY;                    // see TRM section 15.14
  EP2CFG = 0xA2;                // BUF[1:0]=10 for 2x buffering
  
  // EP6 512 BULK IN 2x
  SYNCDELAY;                    //
  EP8CFG = 0xE2;                // BUF[1:0]=10 for 2x buffering
  
  // EP4 and EP6 are not used in this implementation...
  SYNCDELAY;                    //
  EP4CFG = 0x20;                // clear valid bit
  SYNCDELAY;                    //
  EP6CFG = 0x60;                // clear valid bit


////////////  STEP 5 TRM

  SYNCDELAY;
  FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions
  SYNCDELAY;                    // see TRM section 15.14
  FIFORESET = 0x02;             // reset, FIFO 2
  SYNCDELAY;                    // see TRM section 15.14
  FIFORESET = 0x04;             // reset, FIFO 4
  SYNCDELAY;                    // see TRM section 15.14
  FIFORESET = 0x06;             // reset, FIFO 6
  SYNCDELAY;                    //
  FIFORESET = 0x08;             // reset, FIFO 8


  SYNCDELAY;                    //
  OUTPKTEND = 0x82;
  SYNCDELAY;                    //
  OUTPKTEND = 0x82;

  SYNCDELAY;                    //
  EP2FIFOCFG = 0x15;            // AUTOOUT=1, WORDWIDE=1
  
  SYNCDELAY;                    //
  EP8FIFOCFG = 0x0D;            // AUTOIN=1, WORDWIDE=1

  SYNCDELAY;
  EP8AUTOINLENH = 0x02;
  SYNCDELAY;
  EP8AUTOINLENL = 0x00;

  SYNCDELAY;                    // see TRM section 15.14
  FIFORESET = 0x00;             // deactivate NAK-ALL

}

void TD_Init(void)             // Called once at startup
{

    PORTACFG = 0x40;

    REVCTL = 0x03; // REVCTL.0 and REVCTL.1 set to 1
    SYNCDELAY;
  
      CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation
    IFCONFIG = 0xCB; // Configures FX2LP in Slave FIFO mode
    SYNCDELAY;
    EP2CFG = 0xE0; // EP2IN, bulk, size 512, 4x buffered
    SYNCDELAY;
    EP6CFG = 0xA0; // EP6OUT, bulk, size 512, 4x buffered
    SYNCDELAY;

    FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
    SYNCDELAY;
    FIFORESET = 0x02; // reset EP2 FIFO
    SYNCDELAY;
    FIFORESET = 0x06; // reset EP6 FIFO
    SYNCDELAY;
    FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
    SYNCDELAY;

    OUTPKTEND = 0x86; // Arm quattro EP6 buffers to ”prime the pump”
    SYNCDELAY;
    OUTPKTEND = 0x86; // Arm quattro EP6 buffers to ”prime the pump”
    SYNCDELAY;
    OUTPKTEND = 0x86; // Arm quattro EP6 buffers to ”prime the pump”
    SYNCDELAY;
    OUTPKTEND = 0x86; // Arm quattro EP6 buffers to ”prime the pump”
    SYNCDELAY;


    EP6FIFOCFG = 0x00; // AUTOOUT=0
    SYNCDELAY;
    EP6FIFOCFG = 0x11; // AUTOOUT=1
    SYNCDELAY;
    EP2FIFOCFG = 0x09; // AUTOIN=1
    SYNCDELAY;
    PINFLAGSAB = 0xC0; // FLAGA - indexed, FLAGB - EP2FF
    SYNCDELAY;
    PINFLAGSCD = 0x0A; // FLAGC - EP6EF, FLAGD - indexed
    SYNCDELAY;

    EP6AUTOINLENH = 0x02;
    SYNCDELAY;
    EP6AUTOINLENL = 0x00;
    SYNCDELAY;

}

             CSEG AT 0h       ; Reset location
             LJMP Start         ; jump to start Program

             CSEG AT 3h       ; External Interrupt 0 (/INT0)
             RETI
                    
             CSEG AT 0Bh       ; Timer 0 Overflow
             LJMP Timer0_ISR
                    
             CSEG AT 13h       ; External Interrupt 1 (/INT1)
             RETI
                    
            CSEG AT 1Bh       ; Timer 1 Overflow
            RETI
и т.д.