process (fpga_reset_h, sys_clk_int) is
begin
if(fpga_reset_h = '1') then
<...>
ser_txd_reg1 <= '0';
ser_txd_reg2 <= '0';
<...>
elsif(rising_edge(sys_clk_int)) then
<...>
ser_rxd_reg1 <= ser_rxd;
ser_rxd_reg2 <= ser_rxd_reg1;
<...>
end if;
end process;