Release 13.1 Map O.40d (nt)
Xilinx Mapping Report File for Design 'ambpex5_v20_sx50t_core'

Design Information
------------------
Command Line   : map -p 5VSX50TFF1136-1 -o map.ncd -pr b -ol high -cm speed -ir
off -detail -t 1 -global_opt speed -retiming on -equivalent_register_removal on
-lc auto -mt off ambpex5_v20_sx50t_core_merge_chipscope.ngd
ambpex5_v20_sx50t_core_merge_chipscope.pcf
Target Device  : xc5vsx50t
Target Package : ff1136
Target Speed   : -1
Mapper Version : virtex5 -- $Revision: 1.55 $
Mapped Date    : Fri Aug 12 15:37:44 2011

Design Summary
--------------
Number of errors:      0
Number of warnings:   39
Slice Logic Utilization:
  Number of Slice Registers:                 7,789 out of  32,640   23%
    Number used as Flip Flops:               7,779
    Number used as Latches:                      9
    Number used as Latch-thrus:                  1
  Number of Slice LUTs:                      6,463 out of  32,640   19%
    Number used as logic:                    5,405 out of  32,640   16%
      Number using O6 output only:           4,315
      Number using O5 output only:             610
      Number using O5 and O6:                  480
    Number used as Memory:                   1,002 out of  12,480    8%
      Number used as Dual Port RAM:            692
        Number using O6 output only:           656
        Number using O5 and O6:                 36
      Number used as Single Port RAM:           88
        Number using O6 output only:            88
      Number used as Shift Register:           222
        Number using O6 output only:           220
        Number using O5 output only:             1
        Number using O5 and O6:                  1
    Number used as exclusive route-thru:        56
  Number of route-thrus:                       681
    Number using O6 output only:               660
    Number using O5 output only:                19
    Number using O5 and O6:                      2

Slice Logic Distribution:
  Number of occupied Slices:                 3,017 out of   8,160   36%
  Number of LUT Flip Flop pairs used:        9,916
    Number with an unused Flip Flop:         2,127 out of   9,916   21%
    Number with an unused LUT:               3,453 out of   9,916   34%
    Number of fully used LUT-FF pairs:       4,336 out of   9,916   43%
    Number of unique control sets:             365
    Number of slice register sites lost
      to control set restrictions:             541 out of  32,640    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  OVERMAPPING of BRAM resources should be ignored if the design is
  over-mapped for a non-BRAM resource or if placement fails.

IO Utilization:
  Number of bonded IOBs:                         8 out of     480    1%
    Number of LOCed IOBs:                        8 out of       8  100%
    Number of bonded IPADs:                     18
      Number of LOCed IPADs:                    18 out of      18  100%
    Number of bonded OPADs:                     16
      Number of LOCed OPADs:                    16 out of      16  100%

Specific Feature Utilization:
  Number of BlockRAM/FIFO:                      21 out of     132   15%
    Number using BlockRAM only:                 21
    Total primitives used:
      Number of 36k BlockRAM used:              10
      Number of 18k BlockRAM used:              18
    Total Memory used (KB):                    684 out of   4,752   14%
  Number of BUFG/BUFGCTRLs:                      4 out of      32   12%
    Number used as BUFGs:                        4
  Number of BSCANs:                              1 out of       4   25%
  Number of BUFDSs:                              1 out of       6   16%
  Number of DSP48Es:                             4 out of     288    1%
  Number of GTP_DUALs:                           4 out of       6   66%
  Number of PCIEs:                               1 out of       1  100%
  Number of PLL_ADVs:                            1 out of       6   16%

  Number of RPM macros:           12
Average Fanout of Non-Clock Nets:                3.44

Peak Memory Usage:  557 MB
Total REAL time to MAP completion:  8 mins 37 secs
Total CPU time to MAP completion:   8 mins 34 secs

sys_clk_p            => clk125p,   -- тактовая частота 125 MHz от PCI_Express