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Вот скажите мне, где Вы увидели, что при бэканнотации вообще компоненты должны добавляться на схему? Вы сейчас используете какую-то дыру в софте, которая позволяет это делать и требуете, чтобы она работала правильно...
Из хэлпа:
"Backannotating to Allegro Design Entry HDL or System Connectivity Manager
When you swap gates, change properties and constraints, rename reference designators and execute netlist-driven engineering change orders (ECOs) to a layout (that cause it to become logically out of synchronization with its associated schematic), you need to communicate those changes back to the schematic. This process is called backannotation.
Backannotating documents changes to reference designators and physical pin numbers, as well as, properties specified by pxlBA.txt. To perform properly, the design logic and physical layout must match. If parts exist in the schematic that are not in the design (or vice versa) or if schematic connectivity does not match the physical layout, the layout editor identifies these differences.
If you use logic/net logic to create, rename, or remove nets and assign or unassign pins to them, these changes cannot backannotate to the schematic or logic design files. In System Connectivity Manager, only those properties specified in the Setup dialog box in the Property Flow section are also chosen in the backannotate."
Ни о каком добавлении компонентов на схему речь не идет.
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Передача данных из Design в Editor
Sep 22 2011, 06:09
