Схема тактирования всех MCB Spartan-6 от одного тактового источника Опции

[ZZZRF413]

Всем доброго дня!
Посоветуйте пожалуйста по следующему вопросу. Есть плата с Xilinx Spartan-6 FPGA (XC6SLX100T-3FGG676C). Необходимо задействовать все четыре Memory Controller Block от одного тактового сигнала. К 2 MCB подключена память DDR2 800 Mb/s (400 MHz), а к другим двум подключена память LPDDR 400 Mb/s (200 MHz). На ПЛИС заводиться тактовый сигнал 400 МГц.
В User guides я схемы не нашел. Там все просто: частота cX_sys_clk для каждого MCB (или группы из 2) заводиться "с улицы". В IP ядро соответственно встроен IBUFG. Опытным путем я пришел к следующей схеме:
1) Убрал из IP буфер IBUFG перед PLL
2) Подал входную частоту на DCM_SP. Поскольку 400 МГц превышает максимальную входную частоту DCM пришлось задействовать параметр CLKIN_DIVIDE_BY_2. Получилась на выходе частота 200 МГц
3) C этого DCM_SP через BUFG подал частоту на два других DCM_SP, которые располагаются рядом с PLL. Соответственно с этих DCM_SP завел на соответствующий PLL.
4) Поскольку частота разные скорректировал для параметры IP для DDR2 (контроллеры C3 и C4).

Схема в приложении
Проект проходит P&R (трассируется), но по таймингам не проходит(см. приложение). В проекте контроллер LPDDR (контроллеры C5 и C1) не задействован, синтезируется только схема калибровки.
Если DCM_SP не ставить проект не проходит P&R (не трассируется).

Собственно вопрос как побороть эту проблему?
Я вот думаю у меня задан тайминг на входную тактовую частоту, а для остальных ISE сам прописывает. Может там что-нибудь не так и на самом деле все ок? Мне бы не хотелось бы гонятся за черной кошкой в черной комнате...

Эскизы прикрепленных изображений

 

[ZZZRF413]

Добавил в свой .ucf из IP-шного:
CONFIG MCB_PERFORMANCE= EXTENDED;
Стало лучше, теперь только 3 вместо 6 (см. приложение)

Мой .ucf

CODE

# Clock signals
NET "clk" LOC = AC14 |IOSTANDARD = LVCMOS33;

NET "CLK" TNM_NET = "CLK";

#NET "clk0_n" LOC = AF15 | IOSTANDARD = LVPECL_33;
#NET "clk0_p" LOC = AE15 | IOSTANDARD = LVPECL_33;
NET "clk0_n" LOC = AF15 ;
NET "clk0_p" LOC = AE15 ;

# Controll signals
NET "RESET" LOC = AF4 |IOSTANDARD = LVCMOS33;
NET "Start" LOC = W7 |IOSTANDARD = LVCMOS33;
NET "Rev[0]" LOC = AA7 |IOSTANDARD = LVCMOS33;
NET "Rev[1]" LOC = AA6 |IOSTANDARD = LVCMOS33;
NET "Rev[2]" LOC = AF3 |IOSTANDARD = LVCMOS33;
# ADC signals
NET "ADC_SCLK" LOC = H12 |IOSTANDARD = LVCMOS18;
NET "ADC_SDIO" LOC = G13 |IOSTANDARD = LVCMOS18;
NET "ADC1_CSB" LOC = D21 |IOSTANDARD = LVCMOS18;
NET "ADC2_CSB" LOC = D22 |IOSTANDARD = LVCMOS18;
NET "ADC1_D_P[0]" LOC = H8 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[0]" LOC = G8 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[1]" LOC = F7 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[1]" LOC = F6 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[2]" LOC = C3 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[2]" LOC = B3 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[3]" LOC = G6 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[3]" LOC = F5 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[4]" LOC = E6 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[4]" LOC = E5 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[5]" LOC = H9 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[5]" LOC = G9 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[6]" LOC = A3 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[6]" LOC = A2 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[7]" LOC = F9 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[7]" LOC = E8 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[8]" LOC = D5 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[8]" LOC = C5 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[9]" LOC = H10 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[9]" LOC = G10 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[10]" LOC = B4 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[10]" LOC = A4 |IOSTANDARD = LVDS_25;
NET "ADC1_D_P[11]" LOC = F10 |IOSTANDARD = LVDS_25;
NET "ADC1_D_N[11]" LOC = E10 |IOSTANDARD = LVDS_25;
NET "ADC1_OR_P" LOC = B5 |IOSTANDARD = LVDS_25;
NET "ADC1_OR_N" LOC = A5 |IOSTANDARD = LVDS_25;
#NET "ADC1_DCO_P" LOC = J11 | IOSTANDARD = LVDS_25;
#NET "ADC1_DCO_N" LOC = G11 | IOSTANDARD = LVDS_25;
NET "ADC1_DCO_P" LOC = J11 |CLOCK_DEDICATED_ROUTE = FALSE;
NET "ADC1_DCO_N" LOC = G11 |CLOCK_DEDICATED_ROUTE = FALSE;

NET "ADC2_D_P[0]" LOC = K12 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[0]" LOC = J12 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[1]" LOC = J15 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[1]" LOC = H15 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[2]" LOC = J16 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[2]" LOC = J17 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[3]" LOC = F16 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[3]" LOC = E16 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[4]" LOC = G15 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[4]" LOC = F15 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[5]" LOC = F18 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[5]" LOC = E18 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[6]" LOC = G16 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[6]" LOC = F17 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[7]" LOC = F20 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[7]" LOC = E20 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[8]" LOC = H17 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[8]" LOC = G17 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[9]" LOC = C21 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[9]" LOC = B21 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[10]" LOC = H18 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[10]" LOC = H19 |IOSTANDARD = LVDS_25;
NET "ADC2_D_P[11]" LOC = B22 |IOSTANDARD = LVDS_25;
NET "ADC2_D_N[11]" LOC = A22 |IOSTANDARD = LVDS_25;
NET "ADC2_OR_P" LOC = G19 |IOSTANDARD = LVDS_25;
NET "ADC2_OR_N" LOC = F19 |IOSTANDARD = LVDS_25;
#NET "ADC2_DCO_P" LOC = B23 | IOSTANDARD = LVDS_25;
#NET "ADC2_DCO_N" LOC = A23 | IOSTANDARD = LVDS_25;
NET "ADC2_DCO_P" LOC = B23 |CLOCK_DEDICATED_ROUTE = FALSE;
NET "ADC2_DCO_N" LOC = A23 |CLOCK_DEDICATED_ROUTE = FALSE;
# Generator signals
NET "CLK_SCLK" LOC = AD6 |IOSTANDARD = LVCMOS33;
NET "CLK_CS" LOC = AF6 |IOSTANDARD = LVCMOS33;
#NET "CLK_SDO" LOC = W10 | IOSTANDARD = LVCMOS33;
NET "CLK_SDIO" LOC = W9 |IOSTANDARD = LVCMOS33;
# FPGA-DSP Signals
NET "UPP_CHA_WAIT" LOC = A13 |IOSTANDARD = LVCMOS18;
NET "UPP_CHA_ENABLE" LOC = C13 |IOSTANDARD = LVCMOS18;
NET "UPP_CHA_START" LOC = D13 |IOSTANDARD = LVCMOS18;
NET "UPP_CHA_CLK" LOC = E13 |IOSTANDARD = LVCMOS18;
NET "UPP_D[0]" LOC = Y6 |IOSTANDARD = LVCMOS18;
NET "UPP_D[1]" LOC = Y5 |IOSTANDARD = LVCMOS18;
NET "UPP_D[2]" LOC = AB4 |IOSTANDARD = LVCMOS18;
NET "UPP_D[3]" LOC = AC3 |IOSTANDARD = LVCMOS18;
NET "UPP_D[4]" LOC = V7 |IOSTANDARD = LVCMOS18;
NET "UPP_D[5]" LOC = V6 |IOSTANDARD = LVCMOS18;
NET "UPP_D[6]" LOC = U4 |IOSTANDARD = LVCMOS18;
NET "UPP_D[7]" LOC = U3 |IOSTANDARD = LVCMOS18;
NET "UPP_D[8]" LOC = U21 |IOSTANDARD = LVCMOS18;
NET "UPP_D[9]" LOC = T19 |IOSTANDARD = LVCMOS18;
NET "UPP_D[10]" LOC = T20 |IOSTANDARD = LVCMOS18;
NET "UPP_D[11]" LOC = AA23 |IOSTANDARD = LVCMOS18;
NET "UPP_D[12]" LOC = AA24 |IOSTANDARD = LVCMOS18;
NET "UPP_D[13]" LOC = U19 |IOSTANDARD = LVCMOS18;
NET "UPP_D[14]" LOC = U20 |IOSTANDARD = LVCMOS18;
NET "UPP_D[15]" LOC = V20 |IOSTANDARD = LVCMOS18;
NET "SPI0_CLK" LOC = AB14 |IOSTANDARD = LVCMOS33;
NET "UPP_Busy" LOC = AD4 |IOSTANDARD = LVCMOS33;
NET "SPI0_CS" LOC = W8 |IOSTANDARD = LVCMOS33;
NET "SPI0_EN" LOC = AD5 |IOSTANDARD = LVCMOS33;
NET "SPI0_SIMO" LOC = AC6 |IOSTANDARD = LVCMOS33;
NET "SPI0_SOMI" LOC = AC5 |IOSTANDARD = LVCMOS33;
# LPDDR signals
#CONFIG PROHIBIT = N17, H20;
NET "LPDDR1_DQ[0]" LOC = G25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[1]" LOC = G26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[2]" LOC = H24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[3]" LOC = H26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[4]" LOC = E25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[5]" LOC = E26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[6]" LOC = D24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[7]" LOC = D26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[8]" LOC = K24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[9]" LOC = K26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[10]" LOC = J25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[11]" LOC = J26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[12]" LOC = L25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[13]" LOC = L26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[14]" LOC = N25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_DQ[15]" LOC = N26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[0]" LOC = C25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[1]" LOC = C26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[2]" LOC = E24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[3]" LOC = K21 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[4]" LOC = G23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[5]" LOC = M18 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[6]" LOC = M19 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[7]" LOC = E23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[8]" LOC = H21 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[9]" LOC = H22 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[10]" LOC = F22 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[11]" LOC = K19 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[12]" LOC = C24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_A[13]" LOC = B24 | IOSTANDARD = MOBILE_DDR;
#NET "LPDDR1_BA0" LOC = L19 | IOSTANDARD = MOBILE_DDR;
#NET "LPDDR1_BA1" LOC = K20 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_BA[0]" LOC = L19 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_BA[1]" LOC = K20 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_LDM" LOC = J24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_UDM" LOC = J23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_LDQS" LOC = F24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_UDQS" LOC = M24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_RAS" LOC = F23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_CAS" LOC = G24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_WE" LOC = J20 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_CKE" LOC = D23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR1_CK_P" LOC = B25 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "LPDDR1_CK_N" LOC = B26 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "LPDDR1_RZQ" LOC = H20 | IOSTANDARD = LVCMOS18;#| IOSTANDARD = DIFF_MOBILE_DDR;

NET "LPDDR2_DQ[0]" LOC = AA25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[1]" LOC = AA26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[2]" LOC = W25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[3]" LOC = W26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[4]" LOC = U25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[5]" LOC = U26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[6]" LOC = T24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[7]" LOC = T26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[8]" LOC = AD24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[9]" LOC = AD26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[10]" LOC = AB24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[11]" LOC = AB26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[12]" LOC = Y24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[13]" LOC = Y26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[14]" LOC = AE25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_DQ[15]" LOC = AE26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[0]" LOC = P24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[1]" LOC = P26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[2]" LOC = P22 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[3]" LOC = T22 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[4]" LOC = N24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[5]" LOC = U23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[6]" LOC = U24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[7]" LOC = P21 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[8]" LOC = P17 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[9]" LOC = P19 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[10]" LOC = N23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[11]" LOC = N20 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[12]" LOC = N22 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_A[13]" LOC = L23 | IOSTANDARD = MOBILE_DDR;
#NET "LPDDR2_BA0" LOC = R20 | IOSTANDARD = MOBILE_DDR;
#NET "LPDDR2_BA1" LOC = R21 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_BA[0]" LOC = R20 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_BA[1]" LOC = R21 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_LDM" LOC = W24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_UDM" LOC = V23 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_LDQS" LOC = V24 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_UDQS" LOC = AC25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_RAS" LOC = R25 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_CAS" LOC = R26 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_WE" LOC = R18 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_CKE" LOC = N21 | IOSTANDARD = MOBILE_DDR;
NET "LPDDR2_CK_P" LOC = R23 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "LPDDR2_CK_N" LOC = R24 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "LPDDR2_RZQ" LOC = N17 | IOSTANDARD = LVCMOS18;#| IOSTANDARD = DIFF_MOBILE_DDR;
# DDR2 signals
#CONFIG PROHIBIT = H6, AA4; # ZIO
NET "DDR21_DQ[0]" LOC = H3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[1]" LOC = H1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[2]" LOC = G2 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[3]" LOC = G1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[4]" LOC = D3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[5]" LOC = D1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[6]" LOC = E2 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[7]" LOC = E1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[8]" LOC = J2 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[9]" LOC = J1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[10]" LOC = K3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[11]" LOC = K1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[12]" LOC = M3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[13]" LOC = M1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[14]" LOC = N2 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_DQ[15]" LOC = N1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[0]" LOC = L7 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[1]" LOC = L6 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[2]" LOC = K10 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[3]" LOC = M8 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[4]" LOC = J7 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[5]" LOC = L4 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[6]" LOC = L3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[7]" LOC = L10 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[8]" LOC = C2 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[9]" LOC = C1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[10]" LOC = J9 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[11]" LOC = E3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_A[12]" LOC = K8 | IOSTANDARD = MOBILE_DDR;
#NET "DDR21_BA0" LOC = B2 | IOSTANDARD = MOBILE_DDR;
#NET "DDR21_BA1" LOC = B1 | IOSTANDARD = MOBILE_DDR;
#NET "DDR21_BA2" LOC = G3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_BA[0]" LOC = B2 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_BA[1]" LOC = B1 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_BA[2]" LOC = G3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_LDM" LOC = J3 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_UDM" LOC = J4 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_LDQS_P" LOC = F3 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR21_LDQS_N" LOC = F1 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR21_UDQS_P" LOC = L2 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR21_UDQS_N" LOC = L1 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR21_RAS" LOC = L9 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_CAS" LOC = L8 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_WE" LOC = G4 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_CKE" LOC = K9 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_CK_P" LOC = K5 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR21_CK_N" LOC = J5 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR21_ODT" LOC = M6 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_ZIO" LOC = H6 | IOSTANDARD = MOBILE_DDR;
NET "DDR21_RZQ" LOC = M4 | IOSTANDARD = LVCMOS18;#| IOSTANDARD = DIFF_MOBILE_DDR;

NET "DDR22_DQ[0]" LOC = Y3 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[1]" LOC = Y1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[2]" LOC = W2 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[3]" LOC = W1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[4]" LOC = T3 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[5]" LOC = T1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[6]" LOC = U2 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[7]" LOC = U1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[8]" LOC = AA2 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[9]" LOC = AA1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[10]" LOC = AE2 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[11]" LOC = AE1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[12]" LOC = AD3 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[13]" LOC = AD1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[14]" LOC = AB3 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_DQ[15]" LOC = AB1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[0]" LOC = R10 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[1]" LOC = T9 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[2]" LOC = P6 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[3]" LOC = R8 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[4]" LOC = N7 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[5]" LOC = R2 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[6]" LOC = R1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[7]" LOC = N6 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[8]" LOC = R4 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[9]" LOC = R3 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[10]" LOC = N8 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[11]" LOC = N4 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_A[12]" LOC = P8 | IOSTANDARD = MOBILE_DDR;
#NET "DDR22_BA0" LOC = P3 | IOSTANDARD = MOBILE_DDR;
#NET "DDR22_BA1" LOC = P1 | IOSTANDARD = MOBILE_DDR;
#NET "DDR22_BA2" LOC = R5 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_BA[0]" LOC = P3 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_BA[1]" LOC = P1 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_BA[2]" LOC = R5 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_LDM" LOC = W3 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_UDM" LOC = V4 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_LDQS_P" LOC = V3 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR22_LDQS_N" LOC = V1 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR22_UDQS_P" LOC = AC2 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR22_UDQS_N" LOC = AC1 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR22_RAS" LOC = R7 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_CAS" LOC = R6 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_WE" LOC = P5 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_CKE" LOC = R9 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_CK_P" LOC = U5 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR22_CK_N" LOC = T4 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "DDR22_ODT" LOC = T8 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_ZIO" LOC = AA4 | IOSTANDARD = MOBILE_DDR;
NET "DDR22_RZQ" LOC = AB5 | IOSTANDARD = LVCMOS18;#| IOSTANDARD = DIFF_MOBILE_DDR;
# MRAM Signals
NET "MRAM_ADDRESS[0]" LOC = W16 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[1]" LOC = AB19 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[2]" LOC = AA19 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[3]" LOC = V16 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[4]" LOC = U15 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[5]" LOC = AA17 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[6]" LOC = Y17 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[7]" LOC = AB21 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[8]" LOC = AA21 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[9]" LOC = W18 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[10]" LOC = W17 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[11]" LOC = AF22 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[12]" LOC = W19 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[13]" LOC = V18 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[14]" LOC = AC22 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[15]" LOC = AB22 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[16]" LOC = Y20 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[17]" LOC = W20 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[18]" LOC = AF23 |IOSTANDARD = LVCMOS33;
NET "MRAM_ADDRESS[19]" LOC = AA22 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[0]" LOC = AB11 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[1]" LOC = AA10 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[2]" LOC = AB9 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[3]" LOC = AA9 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[4]" LOC = V10 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[5]" LOC = V11 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[6]" LOC = AA11 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[7]" LOC = Y11 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[8]" LOC = Y13 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[9]" LOC = W14 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[10]" LOC = AA12 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[11]" LOC = Y12 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[12]" LOC = AF14 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[13]" LOC = AD14 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[14]" LOC = AF13 |IOSTANDARD = LVCMOS33;
NET "MRAM_DATA[15]" LOC = AE13 |IOSTANDARD = LVCMOS33;
NET "MRAM_E" LOC = Y16 |IOSTANDARD = LVCMOS33;
NET "MRAM_G" LOC = AA18 |IOSTANDARD = LVCMOS33;
NET "MRAM_LB" LOC = AB17 |IOSTANDARD = LVCMOS33;
NET "MRAM_UB" LOC = AA15 |IOSTANDARD = LVCMOS33;
NET "MRAM_W" LOC = AB15 |IOSTANDARD = LVCMOS33;
# LED
NET "LED<0>" LOC = L21 |IOSTANDARD = LVCMOS18;
NET "LED<1>" LOC = L20 |IOSTANDARD = LVCMOS18;
NET "LED<2>" LOC = M21 |IOSTANDARD = LVCMOS18;
NET "LED<3>" LOC = AA3 |IOSTANDARD = LVCMOS18;

NET "test<0>" LOC = G7 | IOSTANDARD = LVCMOS18;
NET "test<1>" LOC = H7 | IOSTANDARD = LVCMOS18;
NET "test<2>" LOC = B12 | IOSTANDARD = LVCMOS18;
NET "test<3>" LOC = A12 | IOSTANDARD = LVCMOS18;
NET "test<4>" LOC = B14 | IOSTANDARD = LVCMOS18;
NET "test<5>" LOC = A14 | IOSTANDARD = LVCMOS18;

CONFIG MCB_PERFORMANCE= EXTENDED;

#Created by Constraints Editor (xc6slx100t-fgg676-3) - 2014/12/25
NET "clk0_p" TNM_NET = clk0_p;
TIMESPEC TS_clk0_p = PERIOD "clk0_p" 2500 ps HIGH 50%;
NET "clk0_n" TNM_NET = clk0_n;
TIMESPEC TS_clk0_n = PERIOD "clk0_n" TS_clk0_p PHASE 1250 ps HIGH 50%;
#TIMESPEC TS_clk0_n = PERIOD "clk0_n" 5000 ps HIGH 50%;
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 20 ns HIGH 50%;
#PIN "CLK_Module/CLK0PLL/PLL_ADV.CLKIN1" CLOCK_DEDICATED_ROUTE = FALSE;
#TIMESPEC TS_clk0_p = PERIOD "clk0_p" 5000 ps HIGH 50%;
#Created by Constraints Editor (xc6slx100t-fgg676-3) - 2014/12/25
#test 200
NET "ADC1_DCO_P" TNM_NET = ADC1_DCO_P;
TIMESPEC TS_ADC1_DCO_P = PERIOD "ADC1_DCO_P" 2500 ps HIGH 50%;
#TIMESPEC TS_ADC1_DCO_P = PERIOD "ADC1_DCO_P" 5000 ps HIGH 50%;
NET "ADC1_DCO_N" TNM_NET = ADC1_DCO_N;
TIMESPEC TS_ADC1_DCO_N = PERIOD "ADC1_DCO_N" TS_ADC1_DCO_P PHASE 1250 ps HIGH 50%;
#TIMESPEC TS_ADC1_DCO_N = PERIOD "ADC1_DCO_N" 2500 ps HIGH 50%;
#TIMESPEC TS_ADC1_DCO_N = PERIOD "ADC1_DCO_N" 5000 ps HIGH 50%;
NET "ADC2_DCO_N" TNM_NET = ADC2_DCO_N;
TIMESPEC TS_ADC2_DCO_N = PERIOD "ADC2_DCO_N" TS_ADC2_DCO_P PHASE 1250 ps HIGH 50%;
#TIMESPEC TS_ADC2_DCO_N = PERIOD "ADC2_DCO_N" 2500 ps HIGH 50%;
#TIMESPEC TS_ADC2_DCO_N = PERIOD "ADC2_DCO_N" 5000 ps HIGH 50%;
NET "ADC2_DCO_P" TNM_NET = ADC2_DCO_P;
TIMESPEC TS_ADC2_DCO_P = PERIOD "ADC2_DCO_P" 2500 ps HIGH 50%;
#TIMESPEC TS_ADC2_DCO_P = PERIOD "ADC2_DCO_P" 5000 ps HIGH 50%;
#test 200

Эскизы прикрепленных изображений

 

[Timmy]

Добавил в свой .ucf из IP-шного:
CONFIG MCB_PERFORMANCE= EXTENDED;
Стало лучше, теперь только 3 вместо 6 (см. приложение)

IP-шный UCF у вас подключён? Там же стоят TIG вроде именно на те пути, где ошибки.