FIFO на VHDL Опции

[Jenya7]

В Квартусе есть корка FIFO вполне такая ничего. Но там единица - байт. А как мне сделать FIFO пакетов по 13 байт?

[Jenya7]

сделал ФИФО

Код

component fifo IS     port
     (
         clock            : in std_logic;
         data            : in std_logic_vector (7 DOWNTO 0);
         rdreq            : in std_logic;
         sclr            : in std_logic;
         wrreq            : in std_logic;
         almost_empty : out std_logic;
         almost_full     : out std_logic;
         empty            : out std_logic;
         full            : out std_logic;
         q               : out std_logic_vector (7 DOWNTO 0);
         usedw            : out std_logic_vector (8 DOWNTO 0)
     );
end component;

U_FIFO : fifo    
   port map
   (
      clock            => REG_CLK,
       data            => fifo_data_in,
       rdreq            => fifo_rdreq,    
       sclr            => '0',
       wrreq            => fifo_wrreq,
       almost_empty  => fifo_almost_empty,
       almost_full     => fifo_almost_full,
       empty            => fifo_empty,
       full            => fifo_full,
       q               => fifo_data_out,
       usedw            => fifo_usedw
   );

Пишу

Код

FIFO_INTERFACE : process (REG_CLK) variable fifo_idx : integer range 0 to 255 := 0;
begin
     if (rising_edge(REG_CLK)) then
          
           case FifoState is
          
               when ST_FIFO_IDLE =>
                
                     fifo_idx := 0;
                      
                      debug_val4 <= fifo_usedw(7 downto 0);
                      
                     if (fifo_write = '1') then
                          if (fifo_almost_full = '0') then
                              FifoState <= ST_FIFO_WRITE;
                         end if;                
                      end if;
            
             when ST_FIFO_WRITE =>     --continious write to FIFO
                     if (cs2 = '0') then   --chip select low
                          if (rx_rdy4 = '1') then  --byte received
                               fifo_wrreq <= '1';
                                 fifo_data_in <= sspi_data_in;
                                 fifo_idx := fifo_idx + 1;
                                 debug_val1 <= debug_val1 + '1';
                             end if;
                            
                           if (fifo_idx > 13) then  --overflow protection
                                fifo_idx := 0;
                               fifo_wrreq <= '0';
                              FifoState <= ST_FIFO_IDLE;
                           end if;        
                      else
                          fifo_idx := 0;
                           fifo_wrreq <= '0';
                          FifoState <= ST_FIFO_IDLE;              
                      end if;            
           end case;  
    
     end if;    
              
end process FIFO_INTERFACE;

Пишу два пакета по 13 байт - debug_val1 = 26 - логично. а debug_val4 = 0 - ноль записанных слов? почему?

Сообщение отредактировал Jenya7 - Aug 5 2018, 13:48