LPC2366, при записи в CCLKCFG все ломается. Опции

[meister]

Никак не пойму, что я делаю не так: при записи 199 (и при записи 1 тоже) в CCLKCFG все ломается. Кварц у меня 3.686МГц.

На МК написано следующее:

Код

LPC2366FBD100
SH3959.1          01
ZSD0743BY

Код

    void init_system_controls_and_status_register(void)
    {
        PCONP = 0;

        // 6.14 PLL setup sequence
        PLLCON_bit.PLLC = 0;
        PLLFEED = hw::PLLFEED_DATA1;
        PLLFEED = hw::PLLFEED_DATA2;
        
        PLLCON_bit.PLLE = 0;
        PLLFEED = hw::PLLFEED_DATA1;
        PLLFEED = hw::PLLFEED_DATA2;

        SCS = BIT_(hw::SCS_GPIOM) | BIT_(hw::SCS_OSCEN);
        while (!SCS_bit.OSCSTAT) {}
        
        CLKSRCSEL = hw::CS_MAIN_OSCILLATOR;
        
        PLLCFG_bit.MSEL = PLL_REGISTER_M - 1;
        PLLCFG_bit.NSEL = PLL_REGISTER_N - 1;
        PLLCON_bit.PLLE = 1;
        PLLFEED = hw::PLLFEED_DATA1;
        PLLFEED = hw::PLLFEED_DATA2;
        
        while (!PLLSTAT_bit.PLOCK) {}
        
        CCLKCFG = 0;        
        CCLKCFG = 199; // до этой строчки стабильно доходит, а через нее - нет

        PLLCON_bit.PLLC = 1;
        PLLFEED = hw::PLLFEED_DATA1;
        PLLFEED = hw::PLLFEED_DATA2;
    }

[amw]

Вот так у меня работает. Правда кварц другой.

Код

void pll_init()
{
    PCONP |= USB_CLK_ON;
    /* 1. Disconnect the PLL with one feed sequence if PLL is already connected. */
    if ( PLLSTAT & (1 << 25) ) {
        PLLCON = 1;
        PLLFEED = 0xAA;
        PLLFEED = 0x55;
    }
    /* 2. Disable the PLL with one feed sequence. */
    PLLCON = 0;
    PLLFEED = 0xAA;
    PLLFEED = 0x55;
    /* 3. Change the CPU Clock Divider setting to speed up operation without the PLL, if desired. */
    CCLKCFG = 0;
    /* 4. Write to the Clock Source Selection Control register to change the clock source. */
    SCS |= 0x20;            /* Enable main OSC */
    while( !(SCS & 0x40) );        /* Wait until main OSC is usable */
    CLKSRCSEL = 1;
    /* 5. Write to the PLLCFG and make it effective with one feed sequence. The PLLCFG can
    only be updated when the PLL is disabled. */
    PLLCFG = (PLL_NVAL << 16) | PLL_MVAL;
    PLLFEED = 0xAA;
    PLLFEED = 0x55;
    /* 6. Enable the PLL with one feed sequence. */
    PLLCON = 1;
    PLLFEED = 0xAA;
    PLLFEED = 0x55;
    /* 7. Change the CPU Clock Divider setting for the operation with the PLL. It's critical to do
    this before connecting the PLL. */
    CCLKCFG = CCLK_VAL;
    USBCLKCFG = USBCLK_VAL;
    /* 8. Wait for the PLL to achieve lock by monitoring the PLOCK bit in the PLLSTAT register,
    or using the PLOCK interrupt, or wait for a fixed time when the input clock to PLL is
    slow (i.e. 32 kHz). The value of PLOCK may not be stable when the PLL reference
    frequency (FREF, the frequency of REFCLK, which is equal to the PLL input
    frequency divided by the pre-divider value) is less than 100 kHz or greater than
    20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time
    has passed. This time is 500 µs when FREF is greater than 400 kHz and 200 / FREF
    seconds when FREF is less than 400 kHz. */
    while (!(PLLSTAT & (1 << 26))){;}
    /* 9. Connect the PLL with one feed sequence. */
    PLLCON = 3;
    PLLFEED = 0xAA;
    PLLFEED = 0x55;
    while ( !((PLLSTAT & (1 << 25))) );    /* Check connect bit status */

    /* Set peripheral clock */
    PCLKSEL0 = PCLK0_WDT(PCLK_1) |
            PCLK0_TIMER0(PCLK_1) |
            PCLK0_TIMER1(PCLK_1) |
            PCLK0_UART0(PCLK_1) |
            PCLK0_UART1(PCLK_1) |
            PCLK0_PWM1(PCLK_1) |
            PCLK0_I2C0(PCLK_1) |
            PCLK0_SPI(PCLK_1) |
            PCLK0_RTC(PCLK_4) |
            PCLK0_SSP1(PCLK_1) |
            PCLK0_DAC(PCLK_1) |
            PCLK0_ADC(PCLK_1) |
            PCLK0_CAN1(PCLK_1) |
            PCLK0_CAN2(PCLK_1) |
            PCLK0_ACF(PCLK_1);

    PCLKSEL1 = PCLK1_BAT_RAM(PCLK_1) |
            PCLK1_GPIO(PCLK_1) |
            PCLK1_PCB(PCLK_1) |
            PCLK1_I2C1(PCLK_1) |
            PCLK1_SSP0(PCLK_1) |
            PCLK1_TIMER2(PCLK_1) |
            PCLK1_TIMER3(PCLK_1) |
            PCLK1_UART2(PCLK_1) |
            PCLK1_UART3(PCLK_1) |
            PCLK1_I2C2(PCLK_1) |
            PCLK1_I2S(PCLK_1) |
            PCLK1_MCI(PCLK_1) |
            PCLK1_SYSCON(PCLK_1);
}