Ethernet + Cyclone + Nios Опции

[yura-w]

Здравствуйте,
хочу сделать устройство: Ethernet (10/100) + CycloneII + NiosII.
Подскажите пожалуйста,
на какую корку (TCP/IP) и соответствующую ей аппаратную часть обратить внимание

[vadimuzzz]

все правильно

[dim99]

Начал "отладку" на плате (cyclone III dev kit).

Удалось запихнуть всю конфигурацию в on-chip(на время для обеспечения работоспособности,потом все пойдет во flash\..) в итоге получилась конфигурация такая:


на топ-левеле в квартусе следующее:


Во время компиляции вылез warning, что будет time-limited sof - нет лицензии на TSE(у кого есть поделитесь ).
После прошивки появилось вот такое окошко:


Зашел в nios ide - запустил на выполнение => run и он выдал ошибку:
panic: stack alloc
dtrap - needs breakpoint

Понятно что проблема со стэком, может ему его мало?
под stack,heap и read\write data memory выделено 52 Кбайта onchip_mem.

Собственно вопрос в чем: как исправить эту ошибку и где найти лицензию на tse(понятно что не за $)

Сообщение отредактировал dim99 - Nov 3 2009, 13:29

[vadimuzzz]

Зашел в nios ide - запустил на выполнение => run и он выдал ошибку:
panic: stack alloc
dtrap - needs breakpoint

Понятно что проблема со стэком, может ему его мало?
под stack,heap и read\write data memory выделено 52 Кбайта onchip_mem.

а проект-то собрался? логи билдера покажите.
да, еще настройки линкера.

[dim99]

а проект-то собрался? логи билдера покажите.
да, еще настройки линкера.

Проект собрался.
Логи sopc builder:

CODE

Info: onchip_mem: Manually-created SOF and simulation initialization files are required for memory onchip_mem.
Info: ext_flash: Flash memory capacity: 64,0 MBytes (67108864 bytes).
Info: prog_mem: Manually-created SOF and simulation initialization files are required for memory prog_mem.
Info: Wrote C:/study/q9/cycloneIII_3c120_fl_eth/niosciii.sopcinfo
Info: tse_mac: HDL generated
Info: tse_mac: Variation name : tse_mac
Info: tse_mac: Variation language : Verilog HDL
Info: tse_mac: Output directory : C:\study\q9\cycloneIII_3c120_fl_eth
Info: tse_mac: Generating HDL...
Info: tse_mac: Generating MegaCore function top-level...
Info: tse_mac: Adding design files to Quartus II project ...
Info: tse_mac: Updating user's project directory...
Info: tse_mac: Generation successful.
Info: tse_mac: HDL generated
Info: niosciii: Generating QIP file.
Info: Info: *******************************************************************
Info: Info: Running Quartus II Shell
Info: Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
Info: Info: Copyright © 1991-2008 Altera Corporation. All rights reserved.
Info: Info: Your use of Altera Corporation's design tools, logic functions
Info: Info: and other software and tools, and its AMPP partner logic
Info: Info: functions, and any output files from any of the foregoing
Info: Info: (including device programming or simulation files), and any
Info: Info: associated documentation or information are expressly subject
Info: Info: to the terms and conditions of the Altera Program License
Info: Info: Subscription Agreement, Altera MegaCore Function License
Info: Info: Agreement, or other applicable license agreement, including,
Info: Info: without limitation, that your use is for the sole purpose of
Info: Info: programming logic devices manufactured by Altera and sold by
Info: Info: Altera or its authorized distributors. Please refer to the
Info: Info: applicable agreement for further details.
Info: Info: Processing started: Tue Nov 03 18:14:42 2009
Info: Info: Command: quartus_sh -t sopc_add_qip_file.tcl
Info: Info: Evaluation of Tcl script sopc_add_qip_file.tcl was successful
Info: Info: Quartus II Shell was successful. 0 errors, 0 warnings
Info: Info: Peak virtual memory: 47 megabytes
Info: Info: Processing ended: Tue Nov 03 18:14:42 2009
Info: Info: Elapsed time: 00:00:00
Info: Info: Total CPU time (on all processors): 00:00:00
Info: Starting PTF file elaboration.
... здесь слишком много написано что включено в проект
Info: Finished elaborating PTF file.
Executing: C:/altera/81/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/study/q9/cycloneIII_3c120_fl_eth/niosciii.ptf
Info: Starting generation...
...
Altera SOPC Builder Version 8.10 Build 163
Copyright © 1999-2008 Altera Corporation. All rights reserved.
# 2009.11.03 18:16:14 (*) mk_custom_sdk starting
# 2009.11.03 18:16:14 (*) Reading project C:/study/q9/cycloneIII_3c120_fl_eth/niosciii.ptf.
# 2009.11.03 18:16:14 (*) Finding all CPUs
# 2009.11.03 18:16:14 (*) Finding all available components
# 2009.11.03 18:16:14 (*) Reading C:/study/q9/cycloneIII_3c120_fl_eth/.sopc_builder/install.ptf
# 2009.11.03 18:16:14 (*) Found 67 components
# 2009.11.03 18:16:15 (*) Finding all peripherals
# 2009.11.03 18:16:16 (*) Finding software components
# 2009.11.03 18:16:16 (*) (Legacy SDK Generation Skipped)
# 2009.11.03 18:16:16 (*) (All TCL Script Generation Skipped)
# 2009.11.03 18:16:16 (*) (No Libraries Built)
# 2009.11.03 18:16:16 (*) (Contents Generation Skipped)
# 2009.11.03 18:16:16 (*) mk_custom_sdk finishing
# 2009.11.03 18:16:16 (*) Starting generation for system: niosciii.
....................
# 2009.11.03 18:16:18 (*) Running Generator Program for cpu
# 2009.11.03 18:16:23 (*) Checking for plaintext license.
# 2009.11.03 18:16:34 (*) Plaintext license not found.
# 2009.11.03 18:16:34 (*) Checking for encrypted license (non-evaluation).
# 2009.11.03 18:16:37 (*) Encrypted license found. SOF will not be time-limited.
# 2009.11.03 18:16:48 (*) Creating encrypted HDL
# 2009.11.03 18:16:51 (*) Running Generator Program for onchip_mem
# 2009.11.03 18:16:55 (*) Running Generator Program for pioInCntrl1
# 2009.11.03 18:16:57 (*) Running Generator Program for pioInCntrl2
# 2009.11.03 18:17:00 (*) Running Generator Program for pioInData
# 2009.11.03 18:17:02 (*) Running Generator Program for pioOutStatus
# 2009.11.03 18:17:04 (*) Running Generator Program for pioOutData
# 2009.11.03 18:17:06 (*) Running Generator Program for sysid
# 2009.11.03 18:17:07 (*) Running Generator Program for ext_flash
# 2009.11.03 18:17:09 (*) Running Generator Program for descriptor_memory
# 2009.11.03 18:17:11 (*) Running Generator Program for sgdma_tx
# 2009.11.03 18:17:14 (*) Running Generator Program for sgdma_rx
# 2009.11.03 18:17:17 (*) Running Generator Program for sys_clk_timer
# 2009.11.03 18:17:18 (*) Running Generator Program for high_res_timer
# 2009.11.03 18:17:20 (*) Running Generator Program for performance_counter
# 2009.11.03 18:17:22 (*) Running Generator Program for button_pio
# 2009.11.03 18:17:24 (*) Running Generator Program for led_pio
# 2009.11.03 18:17:26 (*) Running Generator Program for jtag_uart
# 2009.11.03 18:17:28 (*) Running Generator Program for tse_mem
# 2009.11.03 18:17:30 (*) Running Generator Program for prog_mem
# 2009.11.03 18:17:34 (*) Making arbitration and system (top) modules.
# 2009.11.03 18:17:50 (*) Generating Quartus symbol for top level: niosciii
# 2009.11.03 18:17:50 (*) Symbol C:/study/q9/cycloneIII_3c120_fl_eth/niosciii.bsf already exists, no need to regenerate
# 2009.11.03 18:17:50 (*) Creating command-line system-generation script: C:/study/q9/cycloneIII_3c120_fl_eth/niosciii_generation_script
# 2009.11.03 18:17:50 (*) Running setup for HDL simulator: modelsim
# 2009.11.03 18:17:50 (*) Setting up Quartus with niosciii_setup_quartus.tcl
c:/altera/81/quartus/bin/quartus_sh -t niosciii_setup_quartus.tcl
Info: *******************************************************************
Info: Running Quartus II Shell
Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
Info: Copyright © 1991-2008 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, Altera MegaCore Function License
Info: Agreement, or other applicable license agreement, including,
Info: without limitation, that your use is for the sole purpose of
Info: programming logic devices manufactured by Altera and sold by
Info: Altera or its authorized distributors. Please refer to the
Info: applicable agreement for further details.
Info: Processing started: Tue Nov 03 18:17:54 2009
Info: Command: quartus_sh -t niosciii_setup_quartus.tcl
Info: Evaluation of Tcl script niosciii_setup_quartus.tcl was successful
Info: Quartus II Shell was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 47 megabytes
Info: Processing ended: Tue Nov 03 18:17:59 2009
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:00
# 2009.11.03 18:18:00 (*) Completed generation for system: niosciii.
# 2009.11.03 18:18:00 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED:
SOPC Builder database : C:/study/q9/cycloneIII_3c120_fl_eth/niosciii.ptf
System HDL Model : C:/study/q9/cycloneIII_3c120_fl_eth/niosciii.v
System Generation Script : C:/study/q9/cycloneIII_3c120_fl_eth/niosciii_generation_script
# 2009.11.03 18:18:00 (*) SUCCESS: SYSTEM GENERATION COMPLETED.

Настройки линкера в nios ide?
Посмотрел в preferences nios ide, но что-то не увидел там похожего на свойтсва линковщика ( пока не знаю, где их искать.

Сообщение отредактировал Omen_13 - Nov 6 2009, 16:51

[vadimuzzz]

Проект собрался.
Настройки линкера в nios ide?
Посмотрел в preferences nios ide, но что-то не увидел там похожего на свойтсва линковщика ( пока не знаю, где их искать.

нет,имелись в виду логи NIOS-IDE при сборке проекта. свойства линкера в Project/Properties (или ПКМ на проекте). какие настройки у System Library

[dim99]

Так, выкладываю, что есть - свойства system library:


логи nios ide:
**** Build of configuration Debug for project simple_socket_server_0 ****

make -s all includes
Compiling alt_error_handler.c...
Compiling iniche_init.c...
Compiling led.c...
../led.c: In function `LED7SegLightshowTask':
../led.c:97: warning: unused variable `led_7_seg_val'
Compiling network_utilities.c...
Compiling simple_socket_server.c...
Linking simple_socket_server_0.elf...
Info: (simple_socket_server_0.elf) 326 KBytes program size (code + initialized data).
Info: 1040 Bytes free for stack + heap.
Post-processing to create onchip_mem.hex
Post-processing to create tse_mem.hex
Post-processing to create prog_mem.hex
Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. (Note: This does not affect the instruction set simulator.)
Post-processing to create ext_flash.flash
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