> Похоже в связи с этим введено новое обозначение ПЛИС начиная с Virtex4
Ne sovsem. Stepping Xilinx uge ispolzovala nachinaja s V2. Eto obshij podhod. Predpolagaetsja chto est' polnaja sovmestimost' steppingov snizu vverh.
Kstati budte ostorogny so stepingom. Luchshe vsegda ukazyvat' stepping javno v UCF file, potomu chto ocherednaja novaja versija ISE moget izmanit' "default stepping".
Chto kasaetsja stepping dlja FX60, naprimer:
CES1 - does not have operational MGTs. CES2 - devices have one MGT that is not operational. All the rest up to 3.125 Gbps. CES3 - all MGTs up to 3.125 Gbps. Limited temp range. CES4 - all MGTs up to 6.25 Gbps. Limited temp range. Not avail yet. CES5 - should be final step. All functioning.
Po drugim chipam "stepping record" moget otlichatsja.
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